PMC-Sierra,Inc.
PM5350
S/UNI-155-ULTRA
鈥?Operates in timing master or timing
slave (loop timed) modes.
鈥?Frames to SONET/SDH framing bytes
(A1, A2), processes the section and
line Bit Interleaved Parity (B1, B2) and
the Far-End Block Error (Z2) bytes.
鈥?Interprets the H1, H2, and H3 payload
pointer bytes.
鈥?Processes the SONET path overhead
BIP-8 (B3), signal label (C2) and path
status (G1) bytes.
鈥?Inserts and extracts ATM payloads
using ATM cell delineation.
鈥?Provides on-chip FIFO buffers in both
transmit and receive paths.
鈥?Provides on-chip support for GFC and
XOFF flow control.
鈥?Provides a synchronous 8-bit plus
parity SATURN-Compliant Interface for
PHYsical layer devices (SCI-PHY鈩?
bus operating at 50 MHz.
鈥?Compatible with ATM Forum UTOPIA
interface format.
鈥?Provides a generic 8-bit
microprocessor bus interface for
configuration, control, and monitoring.
鈥?Provides TTL-compatible inputs and
outputs and differential PECL inputs.
鈥?Low power, +5 V CMOS technology.
鈥?Packaged in a 128-pin, 14 mm by
20 mm Plastic Quad Flat Pack (PQFP)
with 0.5 mm lead pitch.
155 Mb/s SATURN User Network Interface
FEATURES
鈥?Low-cost, monolithic SATURN
廬
SONET/SDH ATM User Network
Interface (UNI) for category-5 (UTP-5),
Shielded Twisted Pair (STP) and
optical applications.
鈥?Implements the ATM Transmission
Convergence (TC) sublayer according
to ATM Forum specifications using the
SONET/SDH 155.52 Mb/s STS- 3c/
STM-1 and 51.84 Mb/s STS-1 formats.
鈥?Provides on-chip UTP/STP drivers,
receivers, and line equalizers to allow
direct connection to 155 Mb/s UTP-5
or STP twisted pair wiring facilities
using line coupling transformers.
鈥?Provides a selectable UTP/STP or
Pseudo-ECL (PECL) interface to allow
direct connection to Optical Data Links
(ODLs).
鈥?Includes clock recovery and clock
synthesis with on-chip loop filters.
APPLICATIONS
鈥?155.52 or 51.84 Mb/s twisted pair or
optical ATM LANs
鈥?Workstations and Personal Computer
NIC Cards
鈥?Switches, Hubs, and Router Port
Cards
鈥?SONET- or SDH-Compliant ATM UNIs
BLOCK DIAGRAM
REFCLK
TRREF
TVREF
TGFC
XOFF
TCLK
ATP2
TCP
TFP
Clock
Generator
TXD+
TXD-
Twisted
Pair Tx
Parallel
to
Serial
Transmit
Framer and
Overhead
Processor
Transmit
ATM Cell
Processor
Transmit
ATM
4-Cell FIFO
TSOC
TXPRTY
TDAT[7:0]
TCA
TWRENB
Analog Edge
TFCLK
RSOC
RXPRTY
Serial
to
Parallel
Receive
Framer and
Overhead
Processor
Receive
ATM Cell
Processor
Receive
ATM
4-Cell FIFO
RDAT[7:0]
RCA
RRDENB
RFCLK
TSEN
LED
Control
Microprocessor
Interface
RXD+
RXD-
Twisted
Pair Rx
Clock/Data
Recovery
SD
RCLK
RFP
PECLSEI
OUT[1:0]
RGFC
RCP
RCAP1
RCAP2
PMC-960709 (R4)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS鈥?INTERNAL USE
D[7:0]
A[10:0]
ALE
CSB
WRB
RDB
RSTB
INTB
錚?/div>
1998 PMC-Sierra, Inc.
ATP1
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