48c, and STS-192c traffic.
鈥?/div>
clock synthesis and serializer-
deserializer components.
In quad STS-48/STM-16 mode,
supports four duplex 4-bit 622 MHz
LVDS line side interfaces for direct
connection to external clock recovery,
clock synthesis and serializer-
deserializer components.
Standard OIF SFI-4 (16 x 622 Mbit/s)
line side interface.
Each channel provides termination for
SONET Section, Line and Path
overhead or SDH Regenerator
Section, Multiplexer Section and High
Order Path overhead.
Provides a 16-bit 622 Mbit/s 8B10B
encoded (777.7 MHz) ADD and DROP
serial TelecomBus interface for
grooming a single STS-192/STM-64
stream.
Provides four 4-bit 622 Mbit/s 8B10B
encoded (777.7 MHz) ADD and DROP
serial TelecomBus interfaces for
grooming four STS-48/STM-16
streams.
鈥?Maps SONET/SDH payloads to
system timing, accommodating
plesiochronous timing offsets between
the line and system timing references,
through pointer processing.
鈥?Provides STS-12 cross-connect
capability for grooming traffic at the
ADD and DROP TelecomBus
interface.
鈥?The entire SONET/SDH transport
overhead is extracted to and inserted
from dedicated pins. Path BIP-8 error
counts are extracted to dedicated pins.
鈥?Frames to the SONET/SDH receive
stream, inserts framing bytes and STS
identification into the transmit stream,
and processes or inserts the transport
overhead.
鈥?Interprets or generates the STS (AU)
pointer bytes (H1, H2, H3), extracts or
inserts the synchronous payload
envelope(s) and processes or inserts
the path overhead.
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
BLOCK DIAGRAM
Status
Information
Receive O/H Clock, Frame
Pulse
Receive Transport Overhead
Receive Section/Line DCC and
Clock
B3E
Rx Ring
Control
Port
Transport
Processing Slice x 4
Rx APS
Sync
Extractor
&
Bit Error
Monitor
Path Processing Slice:
192 x STS-1
Path
Trace
Processor
OC-192 Mode:
16 x 777 MHz LVDS
STS-12
XC
8B/10B
Encoder
PISO
LVDS
Transmitter
4 x OC-48 Mode:
4 x 4 x 777 MHz
LVDS
Alarm
Reporting
Section
Trace
Processor
OC-192 Mode:
16 x 622 MHz
LVDS
4 x OC-48 Mode:
4 x 4 x 622 MHz
LVDS
Rx Line
Interface
RX Transport
O/H Processor
Rx Path O/H
Processor
Rx
Telecom
Aligner
SONET/SDH
Alarm
Reporting
Controller
Path
Trace
Processor
Section
Trace
Processor
OC-192 Mode:
16 x 622 MHz
LVDS
4 x OC-48 Mode:
4 x 4 x 622 MHz
LVDS
Tx Line
Interface
Tx Transport
O/H Processor
Tx Path O/H
Processor
Tx
Telecom
Aligner
Tx Pointer
Interpreter
OC-192 Mode:
16 x 777 MHz LVDS
STS-12
XC
8B/10B
Decoder
DRU
LVDS
Receiver
4 x OC-48 Mode:
4 x 4 x 777 MHz
LVDS
Tx Ring
Control Port
JTAG Test
Access Port
Mode
Microprocessor Interface
Control
and
Status
Information
Transmit
Transport
O/H
Test Data
Quad 2488
or 9953
16-bit
Microprocessor
Bus
PMC-2000992 (P2)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS鈥?INTERNAL USE
錚?/div>
Copyright PMC-Sierra, Inc. 2001
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