鈥?/div>
quad STS-12 (STM-
4/AU4/AU3/TU3).
鈥?In single STS-48/STM-16 mode,
supports a duplex 16-bit 155.52 MHz
differential PECL line side interface for
direct connection to external clock
recovery, clock synthesis and
serializer-deserializer components.
鈥?In quad STS-12/STM-4 mode,
supports four duplex 8-bit 77.76 MHz
TTL compatible line side interfaces for
direct connection to external clock
recovery, clock synthesis and
serializer-deserializer components.
鈥?Provides termination for SONET
Section, Line and Path overhead or
SDH Regenerator Section, Multiplexer
Section and High Order Path
overhead.
鈥?In single STS-48/STM-16 mode
provides a 32-bit 77.76 MHz ADD and
DROP TelecomBus.
鈥?In quad STS-12/STM-4 mode provides
four 8-bit 77.76 MHz ADD and DROP
TelecomBus Interfaces.
鈥?Maps SONET/SDH payloads to
system timing, accommodating
plesiochronous timing offsets between
the line and system timing references,
through pointer processing.
鈥?The entire SONET/SDH transport and
path overheads are extracted to and
inserted from dedicated pins.
鈥?Frames to the SONET/SDH receive
stream and inserts framing bytes and
STS identification into the transmit
stream and processes or inserts the
transport overhead.
鈥?Interprets or generates the STS (AU)
pointer bytes (H1, H2, H3), extracts or
inserts the synchronous payload
envelope(s) and processes or inserts
the path overhead.
鈥?Provides Time Slot Interchange (TSI)
function at the ADD and DROP
TelecomBus Interfaces for grooming
any legal mix of SONET/SDH paths.
鈥?Supports Automatic Protection
Switching (APS):
鈥?/div>
Ring control port communication of
path REI and path RDI alarms;
鈥?/div>
Filters the APS channel (K1,K2)
bytes into internal registers; inserts
the APS channel into the transmit
stream.
鈥?Supports line loopback from the line
side receive stream to the transmit
stream and diagnostic loopback from
an ADD TelecomBus interface to a
DROP TelecomBus interface.
鈥?Provides a standard five signal IEEE
1149.1 JTAG test port for boundary
scan board test purposes.
BLOCK DIAGRAM
Status
Information
Receive O/H Clock,
Frame Pulse
Receive Transport
Overhead
Receive Section/Line
DCC and Clock
Receive Path
Overhead
Bit-interleaved
Parity Error
Rx Ring
Control
Port
Rx APS
Sync
Extractor
&
Bit Error
Monitor
Section
Trace
Processor
Path
Trace
Processor
(STS-12) Receive Path Processing Slice
OC-48 Mode:
16-bit x 155.52
Mbit/s PECL
4 x OC-12 Mode:
4 x 8-bit x 77.76
Mbit/s TTL
Rx Line
Interface
RX Transport
O/H Processor
Rx Path O/H
Processor
Rx
Telecom
Aligner
Drop Bus
PRBS
Generator/
Monitor
Rx Timeslot
Interchange
Rx
TelecomBus
System
Interface
OC-48 Mode:
32-bit x 77.76 Mbit/s
TelecomBus
4 x OC-12 Mode:
4 x 8-bit x 77.76
Mbit/s TelecomBus
Alarm
Reporting
SONET/SDH
Alarm
Reporting
Controller
Path
Trace
Processor
(STS-12) Transmit Path Processing Slice
Section
Trace
Processor
OC-48 Mode:
16-bit x 155.52
Mbit/s PECL
4 x OC-12 Mode:
4 x 8-bit x 77.76
Mbit/s TTL
Tx Line
Interface
Tx Transport
O/H Processor
Tx Path O/H
Processor
Tx
Telecom
Aligner
Add Bus Tx Pointer
PRBS
Interpreter
Generator/ (STS/AU-
Monitor
TU3)
Tx
TelecomBus
System
Interface
Tx Timeslot
Interchange
OC-48 Mode:
32-bit x 77.76 Mbit/s
TelecomBus
4 x OC-12 Mode:
4 x 8-bit x 77.76
Mbit/s TelecomBus
Tx Ring
Control Port
JTAG Test
Access Port
Mode
Microprocessor Interface
Transmit O/H
Control
Clock, Frame
and
Pulse
Status
Transmit
Information
Section/Line
DCC Clock
Transmit
Transport
O/H
Transmit Path
O/H
Test Data
Quad 622
or 2488
16-bit
Microprocessor
Bus
PMC-2000326 (p1)
PROPRIETARY AND CONFIDENTIAL TO PMC
-
SIERRA, INC., AND FOR ITS CUSTOMERS鈥?INTERNAL USE
漏 Copyright PMC-Sierra, Inc. 2000
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