PMC-Sierra,Inc.
PM4344
TQUAD
ANSI specifications. Accumulators are
provided for counting, ESF CRC-6
errors, Framing bit errors, Line Code
Violations (LCVs), and Loss Of Frame
(LOF) or change of frame alignment
events.
鈥?Extracts the data link in ESF, T1DM
(DDS), or SLC廬96 modes. Extracts
selected channels.
鈥?Provides a 2-frame elastic store buffer
for jitter and wander attenuation.
鈥?Allows insertion of selected channels
through a serial port.
鈥?Supports transmission of the AIS or
the yellow alarm signal in all formats.
鈥?Provides a digital PLL for generation of
a low jitter transmit clock.
鈥?Provides a FIFO buffer for jitter
attenuation and transmit rate
conversion. FIFO full or empty
indication allows for bit-stuffing in
higher rate multiplexing applications.
Quad T1 Framer
FEATURES
鈥?Monolithic single-chip device that
integrates four full-featured T1 framers
and transmitters for terminating duplex
DS1 signals.
鈥?Supports SF, ESF, T1DM (DDS), and
SLC廬96 format DS1 signals.
鈥?Supports unframed mode. Supports
B8ZS or AMI line codes.
鈥?Supports transfer of PCM and
signalling data to/from 1.544 Mbit/s,
2.048 Mbit/s, 12.352 Mbit/s, or
16.384 Mbit/s backplane buses.
鈥?Supports
n
x DS0 backplane interface
for fractional T1.
鈥?Provides robbed-bit signalling
extraction/insertion, programmable idle
and digital milliwatt code substitution,
and two superframes of signalling
debounce on a per-channel basis.
鈥?Provides trunk conditioning which
forces programmable trouble code
substitution and signalling conditioning
on all/selected channels.
鈥?Provides ESF bit-oriented code
detection/generation, and an HDLC
interface for terminating/generating the
ESF data link.
鈥?Software and functionally compatible
with the PM4341A T1XC Single T1
Transceiver. Pin-compatible with the
PM6344 EQUAD Quad E1 Framer.
鈥?Provides an 8-bit microprocessor bus
interface for configuration, control, and
status monitoring.
鈥?Low power 5 V CMOS technology.
鈥?Available in a rectangular 128-pin
PQFP (14 by 20 mm) package.
TRANSMIT SECTION
鈥?Optionally accepts/provides dual-rail
digital PCM inputs/outputs.
鈥?Provides per-channel minimum ones
density through Bell (bit 7), GTE, DDS,
or 鈥渏ammed bit 8" (56 Kbit/s) zero code
suppression.
鈥?Detects violations of the ANSI T1.403
12.5% pulse density rule over a
moving 192-bit window.
鈥?Allows insertion of framed or un-
framed in-band loopback code
sequences.
鈥?Allows insertion of a data link in ESF,
T1DM (DDS) or SLC
廬
96 modes.
APPLICATIONS
鈥?T1/T3 Multiplexers and Digital Private
Branch Exchanges (PBXs)
鈥?T1 Frame Relay Interfaces
鈥?T1 ATM Interfaces
鈥?Fractional T1 Interfaces
鈥?Digital Access and Cross-Connect
Systems (DACS) and Electronic DSX
Cross-Connect Systems (EDSXs)
鈥?Digital Loop Carriers (DLCs)
鈥?T1 Channel Service Units (CSUs) and
Data Service Units (DSUs)
鈥?ISDN Primary Rate Interfaces (PRIs)
鈥?SONET Add/Drop Multiplexers (ADMs)
BLOCK DIAGRAM
TCLK1[1:4]
BTPCM/
BTDP[1:4]/MTD*
BTSIG/BTDN[1:4]
BTFP[1:4]/MTFP*
BTCLK[1:4]/
MTCLK*
BTIF
Back-
plane
Transmit
Interface
XBAS
Basic Transmitter:
Frame Generation,
Alarm Insertion,
Trunk Conditioning,
Line Coding
TPSC
Per-channel
Controller:
Signal, Idle,
Zero Control
XPDE
Pulse
Density
Enforcer
BRCLK*/MRCLK*
BRFPI*/MRFPI*
MENB*
PMON
Performance
Monitor
Counters
XCLK/VCLK*
FRMR
Framer:
Frame
Alignment,
Alarm
Extraction
RPSC
Per-channel
Controller: Trunk
Conditioning
RDLSIG/
RDLINT[1:4]
RDLCLK/
RDLEOM[1:4]
ELST
Elastic
Store
SIGX
Signalling
Extractor
BRIF
Backplane
Receive
Interface
BRPCM/BRDP[1:4]
BRSIG/BRDN[1:4]
BRFPO[1:4]
MRD*
RCLKO[1:4]
RFP[1:4]
XBOC
Bit-oriented
Code
Generator
XIBC
In-band
Loopback
Code
Generator
XFDL
HDLC
Transmitter
Transmitter
DTIF
Digital
Transmit
Interface
TCLKO[1:4]
TDP/TDD[1:4]
TDN/TFLG[1:4]
DJAT
Digital Jitter
Attenuator
TOPS
Timing
Options
TDLCLK/TDLUDR[1:4]
TDLSIG/TDLINT[1:4]
RECEIVE SECTION
鈥?Recovers clock and data using a digital
PLL for high jitter tolerance.
鈥?Accepts/provides dual- or single-rail
digital PCM inputs/outputs. Accepts
gapped data streams to support higher
rate demultiplexing.
鈥?Provides Loss Of Signal (LOS)
detection, and red, yellow, and Alarm
Indication Signal (AIS) alarm detection.
鈥?Detects violations of the ANSI T1.403
12.5% pulse density rule over a
moving 192-bit window.
鈥?Provides programmable in-band
loopback code detection.
鈥?Supports line and path performance
monitoring according to AT&T and
PMC-941030 (R7)
Receiver
RCLK[1:4]
RDP/RDD[1:4]
RDN/RLCV[1:4]
DRIF
DS-1
Receive
Interface
Internal
Bus
CDRC
Clock and
Data
Recovery
A[9:0]*
RDB*
WRB*
CSB*
ALE*
INTB*
RSTB*
MPIF
Micro-
processor
Interface
IBCD
In-band
Loopback
Code
Detector
PDVD
Pulse
Density
Violation
Detector
ALMI
Alarm
Integrator
FRAM
Framer/Slip
Buffer RAM
RBOC
Bit-oriented
Code
Detector
RFDL
HDLC
Receiver
* These signals are shared between all four framers.
D[7:0]*
錚?/div>
1998 PMC-Sierra, Inc. October, 1998
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