Preliminary
OCTAL T1/E1/J1 Short Haul Line Interface Device
FEATURES
鈥?Monolithic device which integrates 8
T1/J1 or E1 short haul line interface
circuits.
鈥?Software-selectable between T1/J1 and
E1 operation on a per-device basis.
鈥?Meets or exceeds T1/J1 and E1 short
haul network access specifications
including ANSI T1.102, T1.403,
T1.408, AT&T TR 62411, ITU-T G.703,
G.704 as well as ETSI 300-011, CTR-
4, CTR-12 and CTR-13.
鈥?Provides encoding and decoding of
B8ZS, HDB3 and AMI line codes.
鈥?Provides clock recovery and line
performance monitoring.
鈥?Provides transmit and receive jitter
attenuation.
鈥?Provides support for redundancy.
鈥?Provides digitally programmable pulse
templates.
鈥?Provides a selectable, per channel
independent de-jittered T1 or E1
recovered clock for system timing and
redundancy.
鈥?Provides PRBS generators and
detectors on each tributary for error
testing at DS1 and E1 rates as
recommended in ITU-T O.151.
鈥?Provides an 8-bit microprocessor bus
interface for configuration, control, and
status monitoring.
鈥?Provides line and digital loopback modes.
鈥?Supports programmable inband
loopback codes.
鈥?Uses line rate system clock.
鈥?Provides an IEEE 1149.1 (JTAG)
compliant test access port (TAP) and
controller for boundary scan test.
鈥?Provides a microprocessor-readable
general purpose input pin and a
microprocessor-writable general
purpose output pin.
PM4319
OCTLIU-SH
SYSTEM INTERFACE
鈥?High-density SBI bus interface.
Supports seamless interconnection of
up to 11 OCTLIU-SHs to TE-32,
TEMAP-84 and AAL1gator-32 using
only 27 wires.
RECEIVE SECTION
鈥?Supports T1 signal reception at 772
kHz and E1 signal reception at 1.024
MHz for distances with up to 6 dB of
cable attenuation.
鈥?Performs B8ZS or AMI decoding when
processing a bipolar DS-1 signal, and
HDB3 decoding when processing a
bipolar E1 signal.
鈥?Tolerates more than 0.3 UI peak-to-
peak, high frequency jitter as required
by AT&T TR 62411 and Bellcore TR-
TSY-000170.
鈥?Detects line code violations, B8ZS/
HDB3 line code signatures, loss of
signal, and successive zeroes
conditions.
鈥?Supports G.772 compliant non-
intrusive protected monitoring points.
POWER
鈥?Implemented in a low power 3.3 V
tolerant 1.8/3.3 V CMOS technology.
PACKAGE
鈥?Available in a high density 288-pin
Tape-SBGA (23 mm x 23 mm) package.
鈥?Provides a -40 擄C to +85 擄C industrial
temperature operating range.
BLOCK DIAGRAM
TXTIP1[8:1]
TXTIP2[8:1]
TXRING1[8:1]
TXRING2[8:1]
XLPG
Transmit LIU
TJAT
Digital Jitter
Attenuator
LCODE
AMI / B8ZS /
HDB3 Line
Encoder
XPDE
Pulse Density
Enforcer
XIBC
Inband Loop-
back Code
Generator
ADATA[7:0]
Tx Data
Tx Clock
EXSBI-8
SBI Extract
ADP
APL
AV5
(Diagnostic
Digital
Loopback)
PMON
Performance
Monitor
(Line
Loopback)
Rx Data
INSBI-8
RXTIP[8:1]
RXRING[8:1]
RLPS
Receive LIU
CDRC
Clk/Data
Recovery
PDVD
Pulse Density
Viol. Detector
IBCD
Inband Loop -
back Code
Detector
RJAT
Digital Jitter
Attenuator
SBI Insert
Rx Clock
PRBS
Pattern
Generator /
Detector
REFCLK
AC1FP
DC1FP
C1FPOUT
DDATA[7:0]
DDP
DPL
DV5
DACTIVE
LIU Octant x 8
TXHIZ/LLB
RSTB
XCLK
RSYNC
CSD
Clock
Synthesis /
Distribution
TOPS
Timing
Options
LOS
Serial
Output
JTAG
uP Interface
D[7:0]
A[10:0]
ALE
CSB
WRB
RDB
INTB
PI
PO
LOS
LOS_L1
TCK
TMS
TDI
TDO
TRSTB
PMC-2012171 (p2)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS鈥?INTERNAL USE
漏 Copyright PMC-Sierra, Inc. 2001
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