PMC-Sierra,Inc.
PM3390
鈥?Each chip supports the EXACT Bus
Protocol, which is a 10-bit,
unidirectional insertion ring running at
125 MHz or 135 MHz.
鈥?EXACT Bus ports allow simple box-to-
box, card-to-card, or chip-to-chip
interconnect.
鈥?8B/10B EXACT Bus encoding is
compatible with Common Serialization
(SERDES) devices to allow serial
extension using coax or twinax cable.
鈥?Management interface connects to an
off-chip microprocessor for access to
internal control registers.
Octal EXACT鈩?Bus Switch Matrix
FEATURES
鈥?Sixteen Gbit/s, protocol-independent
switching matrix expandable to 32 Gbit/s.
鈥?Provides eight gigabit, full-duplex
EXACT鈩?Bus ports that each support an
EXACT switch port controller.
鈥?Provides non-blocking connection
between eight EXACT Bus (Ethernet
Switching, Access, Control, and
Termination) rings.
鈥?Supports non-blocking connections
between sixteen EXACT Bus rings to
provide a system bandwidth of
32 Gbit/s using four PM3390 devices.
鈥?Destination lookup table maps logical
EXACT ports to physical PM3390 ports.
Destination lookup table can be
dynamically allocated.
鈥?Provides visibility into internal dataflow to
allow external flow control in systems that
do not use the EXACT Bus link protocol.
PACKAGING
鈥?Provides a standard five signal
P1149.1 JTAG test port for boundary
scan board test purposes.
鈥?Implemented in low power 3.3 V,
CMOS technology.
鈥?Available in a 352-pin Ball Grid Array
(BGA) package.
APPLICATIONS
鈥?High Bandwidth (16 to 32 Gbit/s)
Ethernet Switches that Support
Combinations of 10/100/1000 Ports.
鈥?Multiprotocol Switch (Ethernet, ATM,
Packet Over SONET, FDDI, and TR)
鈥?Modular Ethernet Switches.
鈥?Fixed-configuration Ethernet Switches.
COMPATIBILITY
鈥?Interworks with the following EXACT
Chipset devices:
PM3370 Octal 10/100 Ethernet Switch
Port Controller with MII interfaces.
PM3380 Gigabit Ethernet Switch Port
Controller.
BLOCK DIAGRAM
8
脳
EXACT
Input Ports
8
脳
EXACT
Output Ports
XRXD[9:0]
XRCLK
Per Port
Signals
EXACT
8 Input
Buffers
Pipelined
Data
Mux
Cell
Central
Store
Pipelined
Data
Mux
EXACT
8 Output
Buffers
XTXD[9:0]
XTCLK
Per Port
Signals
Free List
Manager
Cell List
Manager
JTAG
Control
Interface
Management
Interface
Expansion
Contol
4 Port
Expansion
Interface
SYSCLK
XREFCK135
XREFCK125
RESETI
INT
NFLOW[3:0]
MI_AD[15:0]
MI_ALE
MI_RD
MI_WR
MI_CS
XFLOWI
XFLOWO
XSTATI
XSTATO
XFRAMEI
XFRAMEO
TDI
TDO
TMS
TCK
TRSTB
EXRXD[8:0]
EXRXCLK
PMC-980237 (R5)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS鈥?INTERNAL USE
漏
1999 PMC-Sierra, Inc.
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