PM3386
S/UNI廬-2xGE
Dual Gigabit Ethernet Controller
FEATURES
鈥?Two port full-duplex Gigabit Ethernet
Controller with an industry standard
POS-PHY Level 3鈩?system interface.
鈥?Provides direct connection to optics.
鈥?Connection to copper Gigabit Ethernet
physical layer devices via two GMII
interfaces.
鈥?Incorporates dual SERDES,
compatible to IEEE 802.3 1998 PMA
physical layer specification.
鈥?Supports dual IEEE 802.3 -1998
GMII/TBI interfaces for connection to
copper Gigabit Ethernet physical layer
devices.
鈥?Provides dual standard IEEE 802.3
Gigabit Ethernet MACs for frame
verification.
鈥?Provides on-chip data recovery and
clock synthesis.
鈥?Provides eight unicast exact-match
address filters to filter frames based on
DA, SA, or VID.
鈥?Each address filter can indicate
whether to accept or discard based on
a match.
鈥?Provides 64-group multicast address
filter.
鈥?Internal 16 kbyte TX and 64 kbyte RX
FIFOs to accommodate system
latencies.
鈥?SATURN廬 compatible interface for
Packet-Over-SONET Physical Layer
and Link Layer devices Level 3 (POS-
PHY Level 3 system interface).
鈥?Line side loopback for system level
diagnostic capability.
鈥?16 bit generic microprocessor interface
for device initialization, control, register
and per port statistics access.
鈥?Minimum frame size 64 bytes. Supports
jumbo frames up to 9.6 kbytes.
鈥?Supports big endian data formats.
鈥?Programmable inter-packet gap (IPG).
鈥?Loopback for diagnostic capability
through GMAC.
鈥?Minimum 58 minutes before rollover.
鈥?Provides statistic counters to support
SNMP and RMON implementations.
POS-PHY LEVEL 3 SYSTEM
INTERFACE
鈥?Standard OC-48 bandwidth
Packet/Cell interface.
鈥?Compatible with PMC-Sierra devices
supporting POS-PHY Level 3, including:
鈥?/div>
PM5381 S/UNI廬-2488 ATM and
POS physical layer device.
鈥?/div>
PM5358 S/UNI廬-4x622 single
channel OC-48c device with
integrated analog.
鈥?/div>
PM7390 S/UNI-MACH-48 multi-
service access device for
channelized interfaces.
鈥?/div>
PM5382 S/UNI-16x155 sixteen
channel OC-3c framer with
integrated analog and POS-PHY
Level 3 and UTOPIA Level 3
interface.
鈥?POS-PHY Level 3 provides connection
to upper layer device at data rates up
to 2,400 Mbit/s.
FLOW CONTROL
鈥?Option to support IEEE 802.3-1998
flow control at each Ethernet port.
鈥?Programmable watermarks for
full/empty FIFO conditions.
鈥?Automatic generation of pause frames
based on FIFO fill levels.
鈥?Upper layer device can flow control
Ethernet ports using side-band or host
signaling to cause generation of a
Pause frame.
鈥?Provides per-port side-band Pause
state indication for upstream devices.
鈥?Loss-less flow control on all valid
frames up to 9.6 kbytes.
STATISTICS
鈥?40 bit counters are used to ensure
rollover compliance with
IEEE 802.3-1998.
BLOCK DIAGRAM
POS-PHY
Level 3
PAUSE [1:0]
PAUSED [1:0]
RFCLK
RENB
RDAT[31:0]
RMOD[1:0]
RPRTY
RVAL
RSOP
REOP
RERR
RSX
MDC
MDIO
RX_CLK
RX_DV
RX_ER
RXD [7:0]
GTX_CLK
TX_EN
TX_ER
TXD [7:0]
Ethernet Statistics
Enhanced Gigabit MAC
Flow Ctrl /
Auto-Negotiation
Address
Filtering
Ingress
Interface
GMII
Interface
POS
PHY
Ingress
FIFO
Gigabit
Media
Access
Controller
GIGABIT ETHERNET MAC
鈥?Verifies frame integrity (FCS and
length checks).
鈥?Errored frames can be filtered or
passed to a higher layer device.
鈥?Automatic Base Page Autonegotiation,
extended Autonegotiation (Next Page)
supported via host.
鈥?Egress Ethernet frame encapsulation
(pad to minimum size, add preamble,
IFG and CRC generation).
鈥?Supports Ethernet 2.0, IEEE 802.3 LLC
and IEEE 802.3 SNAP/LLC encoding
formats, and VLAN tagged frames.
RXD +/-
Data Recovery/
Serial to Parallel
8B/10B
Encoder/
Decoder
Egress
Interface
DTPA[1:0]
STPA
PTPA
TADR
TFCLK
TENB
TDAT[31:0]
TMOD[1:0]
TPRTY
TSOP
TEOP
TERR
TSX
SD
CLK125
PLL Clock
Multiply
TXD +/-
Parallel to Serial
SERDES
PCS
MAC
POS
PHY
Egress
FIFO
ATP[3:0]
Microprocessor
Interface
JTAG
PMD_SEL [1:0]
RSTB
ALE
CSB
WDB
RDB
TRSTB
TMS
INTB
A [11:0]
PMC-1991223 (R4)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS鈥?INTERNAL USE
D [15:0]
TDO
TCK
TDI
漏 Copyright PMC-Sierra, Inc. 2001
1
2
