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PLUTO

Dual Mode CDMA/AMPS Baseband Interface

Advance Information

DS4722 - 1.8 July 1998

The PLUTO baseband interface circuit is designed for use

in dual mode CDMA/AMPS digital cellular telephones. In the

telephone, Pluto provides the interface between the radio (RF

& IF) components and the baseband digital signal processor.

Pluto is part of a complete chipset solution for CDMA phones

entitled the Planet chipset.

The receive (RX) section converts the analog in-phase and

quadrature (I & Q) signals into equivalent digital signals whilst

the transmit (TX) circuits perform the complementary function

of translating digital baseband information into the analog

equivalent signals required for the modulator in the radio

circuits. VHF PLLS are also included for second RXLO and

TXIF generation.

PLUTO also contains a 4 channel general purpose ADC

which is included for such purposes as environmental and

signal strength monitoring.

PIN 1 IDENT

PIN 80

FEATURES

s

Dual mode AMPS/CDMA compatible

s

Low Power/Low Voltage operation

s

Standard baseband I and Q interface

s

4 Input Auxiliary ADC

s

Synthesisers

APPLICATIONS

s

Dual Mode CDMA/AMPs digital cellular

telephones

TXQ,TXQ-

FM_MOD

TXI,TXI-

TXIF PD_RX

PD_TX

RXIF

PIN 1

GP80

MP28

Figure 1 Pin connections - top view

ABSOLUTE MAXIMUM RATINGS

Supply voltage

Voltage applied to any other pin

Operating junction temperature

Storage temperature

ESD (human body model)

ORDERING INFORMATION

PLUTO/KG/GP1R

ADC<3> ADC<1>

FC_I

I+,I-

BAL

Q+,Q-

FC_Q

ADC<2> ADC<0>

-0.3 to 3.9V

-0.3 to Vcc+0.3V

150擄C

-55擄C to 150擄C

2kV

TX

SYNTH

TCXO/4

/4

RX

SYNTH

8-BIT

DAC

8-BIT

DAC

8-BIT

DAC

ANALOG

MULTIPLEXER

S<0>

S<1>

VDD

GND

1025

CHIPx8

512

8-BIT

DAC

8-BIT

DAC

8-BIT 6-BIT

ADC ADC

6-BIT 8-BIT

ADC ADC

8-BIT

ADC

SUB

FM/

SLEEP/

IDLE/

RESET/

19.68MHz

BUFFER

tx calibration and control

rx calibration and control

SDATA

SCLOCK

TCXO

TXCLK

TXD<7:0>

RXIFMDATA

RXID<3:0>

ADCENA

ADCDATA

ADCCLK

RXQFMDATA

RXQD<3:0>

SLATCH

Figure 2 Block diagram

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