T3 Framer MegaCore
Function (T3FRM)
August 2001; ver. 1.02
Data Sheet
Features
Achieving optimum performance in the Altera
廬
APEX
TM
20K device
architecture, the multi-featured T3 Framer MegaCore
廬
Function (T3FRM)
meets your innovative design needs, and provides fast time-to-market
release for increased productivity. The T3FRM features include:
I
I
I
I
I
I
Extraction and formatting of data for T3 line;
Support of nominal T3 data rates of 44.736 megabits per second
(Mbps);
Five interfaces provide connections to other devices, including a
serial connection to a T3 mapper;
The T3FRM complies with all applicable standards, including:
鈥?/div>
Telcordia,
Transport Systems Generic Requirements (TSGR):
Common Requirements GR-499-CORE,
Issue 2, December 1998
鈥?/div>
American National Standards Institute,
Digital Hierarchy-Formats
Specifications T1.107-1995
鈥?/div>
Altera Corporation,
Atlantic
TM
Interface Functional Specification
Easy-to-use MegaWizard
廬
Plug-In customizes your MegaCore
function. Quartus
廬
II software and OpenCore
廬
feature allow place-
and-route, and static timing analysis of designs prior to licensing;
Secure register transfer level (RTL) simulation models allow
simulation of the user design in third-party simulators.
Generating
Variants
Table 1. Optional Features
Table 1
shows the optional features available to generate all variants.
Note (1)
Options
Parameters
鈥?/div>
HDLC
Choices
鈥?/div>
Y/N
LEs
1,301
571
ESBs
0
2
Basic Configuration
HDLC Controller鈥擳ransmit and receive HDLC controllers with data FIFO
buffer to process overhead bit HDLC channel
Note:
(1)
The logic element (LE) and embedded system block (ESB) numbers are approximate as of August, 2001. Users are
strongly advised to run the MegaWizard Plug-In and the Quartus II software to see exact numbers for each T3FRM.
1
A-DS-IPT3FRM-1.02
Altera Corporation
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