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PLL2124X Datasheet

  • PLL2124X

  • PLL2124X 50MHz ~ 300MHz FSPLL|Data Sheet

  • 10頁

  • ETC

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50MHz ~ 300MHz FSPLL
GENERAL DESCRIPTION
The pll2124x is a Phase Locked Loop (PLL)
frequency synthesizer. The PLL provides frequency
multiplication capabilities. The output clock frequency
FOUT is related to the input clock frequency FIN by
the following equation:
PLL2124X
Ver 1.0.0. (July, 2002)
FEATURES
鈥?/div>
0.13um CMOS device technology
鈥?1.5 Volt single power supply
鈥?Output frequency range: 50M ~ 300MHz
鈥?Jitter: 鹵150ps at 300MHz (typ.)
鈥?Duty ratio: 40% to 60% (All tuned range)
FOUT=(m*FIN) / (p*2 )
Where FOUT is the output clock frequency. FIN is
the input clock frequency. m, p and s are the values
for programmable dividers. pll2124x consists of a
Phase Frequency Detector(PFD), a Charge Pump, an
Off-chip Loop Filter, a Voltage Controlled Oscillator
(VCO), a 6bit Pre-divider, an 8bit Main-divider and
2bit Post-scaler as shown in functional block diagram.
s
鈥?Power down mode
鈥?Off-chip loop filter
鈥?Frequency is changed by programmable divider
NOTE
1.
Don't set the P or M value as zero, that is, seting the P=000000, M=00000000 can cause malfunction of the PLL.
2. The proper range of P and M : 1<=P<=62, 1<=M<=248
3. The P and M must be selected considering stability of PLL and VCO output frequency range.
4.
Please contact SEC application engineer for proper selection of the P, M, S values of the PLL.
No responsibility is assumed by SEC for its use nor for any infringements of patents or other rights of third parties that
may result from its use. The contents of the datasheet is subject to change without any notice.
FUNCTIONAL BLOCK DIAGRAM
AVDD15D
Fin/P
AVSS15D
UP
FILTER
R1
Charge
Pump
DN
FIN
Pre-Divider
(P)
Fvco/M
Phase
Frequency
Detector
C2
6b
M[7:0]
P[5:0]
S[1:0]
8b
PWRDN
Post - Scaler
(S)
(1,2,4,8)
VABB
2b
FOUT
Main-Divider
(M)
Fvco
Voltage
Controlled
Oscillator
Vctrl
AVDD15A
AVSS15A
SAMSUNG ELECTRONICS Co. LTD

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