音影先锋亚洲天堂网|电影世界尽头的爱完整版播放|国产 熟女 91|高清无码免费观看欧美日韩|韩国一区二区三区黄色录像|美女亚洲加勒比在线|亚洲综合网 开心五月|7x成人在线入口|成人网站免费日韩毛片区|国产黄片?一级?二级?三级

PLL2099X Datasheet

  • PLL2099X

  • PLL2099X 20MHz ~ 300MHz FSPLL|Data Sheet

  • 55.59KB

  • 10頁(yè)

  • ETC

掃碼查看芯片數(shù)據(jù)手冊(cè)

上傳產(chǎn)品規(guī)格書(shū)

PDF預(yù)覽

20MHz ~ 300MHz FSPLL
General Description
The pll299x is a Phase-Locked Loop (PLL) frequency
synthesizer constructed in CMOS on single monolithic
structure. The PLL macro-functions provide frequency
multiplication capabilities.
The output clock frequency FOUT is related to the
input clock frequency FIN by the following
equation:
^
FOUT=(m*FIN) / (p*2 s)
Where, FOUT is the output clock frequency.
FIN is the input clock frequency.
m, p and s are the values for programmable dividers.
pll2099x consists of a Phase/Frequency Detector(PFD),
a Charge Pump, an Internal Loop Filter, a Voltage
Controlled Oscillator(VCO), a 6bit Pre-divider, an 8bit
Main divider and 2bit Post Scaler as shown in Figure1.
PLL2099X
Ver 1.1 ( Nov. 2001 )
F ea ture s
鈥?/div>
0.18mm CMOS device technology
鈥?1.8 Volt single power supply
鈥?Output frequency range: 20 ~ 300 MHz
鈥?Jitter 鹵120ps at 300MHz
鈥?Duty ratio 45% to 55% (All tuned range)
鈥?Frequency changed by programmable divider
鈥?Power down mode
FUNCTIONAL BLOCK DIAGRAM
FIN
Pre
Divider
PFD
Charge
PUMP
VCO
Post
Scaler
FOUT
FILTER
Main
Divider
Figure1 : Phase Locked Lock Loop Block Diagram
No responsibility is assumed by SEC for its use nor for
any infringements of patents or other rights of third parties
that may result from its use. The contents of the datasheet
is subject to change without any notice.
SAMSUNG ELECTRONICS Co. LTD

PLL2099X相關(guān)型號(hào)PDF文件下載

掃碼下載APP，
一鍵連接廣大的電子世界。

在線人工客服

買(mǎi)家服務(wù)：
賣(mài)家服務(wù)：
技術(shù)客服：

0571-85317607

網(wǎng)站技術(shù)支持

13606545031

客服在線時(shí)間周一至周五
9:00-17:30

關(guān)注官方微信號(hào)，
第一時(shí)間獲取資訊。

建議反饋

聯(lián)系人：

聯(lián)系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫(kù)提出的寶貴意見(jiàn)，您的參與是維庫(kù)提升服務(wù)的動(dòng)力！意見(jiàn)一經(jīng)采納，將有感恩紅包奉上哦！