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PLL2080X Datasheet

  • PLL2080X

  • PLL2080X 0.35um40MHz De-Skew PLL PLL2080X|Data Sheet

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0.35
摟-
40MHz De-Skew PLL
40MHz PLL ASIC Core
PLL2080X
DECEMBER 1998. Ver1.0
The PLL2080X PLL is an application specific PLL designed for the requirements of one customer.
The core PLL is a standard 80MHz ring oscillator design with a phase frequency detector. Divide
ratios and feedback paths are designed specific to the customers needs.
Features
鈥?/div>
3.3V operations in the Samsung 0.35um process
鈥?/div>
Core PLL jitter less than
鹵
200ps
鈥?/div>
20MHz clock input matched in phase to 40MHz clock output
鈥?/div>
Selectable feedback matching paths
Functional Block Diagram
CLKIN
MODE
REFCLK
1
Divide 2
0
Clock
Input
Matched
Delay
PFD
Charge
Pump
RCPLL
Clock
Tree
Matched
Delay
Divide 2
VCO
Differential
Ring Oscillator
CLKOUT
Figure 1. Functional Block Diagram
Pin Description
Pin Name
VDD
VSS
CLKIN
REFCLK
CLKOUT
MODE
RCPLL
3.3V
鹵
5% PLL Supply
0V PLL Ground
External Clock Input to PLL
Duty Cycle : 40%~60%
Feedback clock input to PLL from reference point on internal device clock tree
PLL output clock
Mode=1, select to REFCLK / Mode=0, select to Match Delay
Point of connection to external discrete loop filter
Description
1 / 5

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