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PLL2076X Datasheet

  • PLL2076X

  • PLL2076X 50MHz~500MHz FSPLL|Data Sheet

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50MHz~500MHz FSPLL
GENERAL DESCRIPTION
The pll2076x is a Phase Locked Loop (PLL)
frequency synthesizer. The PLL provide frequency
multiplication capabilities. The output clock frequency
FOUT is related to the input clock frequency FIN by
the following equation:
PLL2076X
Ver 1.2
FEATURES
鈥?/div>
0.18um CMOS device technology
鈥?1.8 Volt single power supply
鈥?Output frequency range: 50M ~ 500MHz
鈥?Jitter: 鹵120ps at 500MHz
鈥?Duty ratio: 40% to 60% (All tuned range)
FOUT=(m*8*FIN) / (p*2 )
Where FOUT is the output clock frequency. FIN is
the input clock frequency. m, p and s are the values
for programmable dividers. pll2076x consists of a
Phase Frequency Detector(PFD), a Charge Pump, an
Off-chip Loop Filter, a Voltage Controlled Oscillator
(VCO), a 6bit Pre-divider, an 6bit Main-divider and
2bit Post-scaler as shown in functional block diagram.
s
鈥?Power down mode
鈥?Off-chip loop filter
鈥?Frequency is changed by programmable divider
NOTE
1.
Don't set the P or M as zero, that is 000000 / 000000
2. The proper range of P and M : 1<=P<=62, 1<=M<=62
3. The P and M must be selected considering stability of PLL and VCO output frequency range
4. Please consult with SEC application engineer to select the proper P, M and S values
No responsibility is assumed by SEC for its use nor for any infringements of patents or other rights of third parties that
may result from its use. The contents of the datasheet is subject to change without any notice.
FUNCTIONAL BLOCK DIAGRAM
AVDD18D
Fin/P
AVSS18D
UP
FILTER
R1
Charge
Pump
DN
FIN
Pre-Divider
(P)
Fvco/M
Phase
Frequency
Detector
C2
6b
M[5:0]
P[5:0]
S[1:0]
6b
PWRDN
Post - Scaler
(S)
(1,2,4,8)
AVDD18A
AVSS18A
VABB
2b
FOUT
Main-Divider
(M)
Fvco
1/8
Voltage
Controlled
Oscillator
Vctrl
SAMSUNG ELECTRONICS Co. LTD

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