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PLL2073X Datasheet

  • PLL2073X

  • PLL2073X 20MHz ~ 300MHz FSPLL|Data Sheet

  • 11頁

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20MHz ~ 300MHz FSPLL
General Description
The pll2073x is a Phase-Locked Loop (PLL) frequency
synthesizer constructed in CMOS on single monolithic
structure. The PLL macro-functions provide frequency
multiplication capabilities.
The output clock frequency FOUT is related to the
input clock frequency FIN by the following
equation:
FOUT=(m*FIN) / (p*2
^
S)
Where, FOUT is the output clock frequency.
FIN is the input clock frequency.
m, p and s are the values for programmable dividers.
pll2073x consists of a Phase/Frequency Detector(PFD),
a Charge Pump, an Internal Loop Filter, a Voltage
Controlled Oscillator(VCO), a 6bit Pre-divider, an 8bit
Main divider and 2bit Post Scaler as shown in Figure1.
PLL2073X
Ver 1.5_5
Features
鈥?/div>
0.18um CMOS device technology
鈥?1.8 Volt single power supply
鈥?Output frequency range: 20 ~ 300 MHz
鈥?Jitter 鹵120ps at 300MHz
鈥?Duty ratio 45% to 55% (All tuned range)
鈥?Frequency changed by programmable divider
鈥?Power down mode
NOTE
1.
Don't set the P or M as zero, that is 000000 / 00000000
2. The proper range of P and M : 1<=P<=62, 1<=M<=248
3. The P and M must be selected considering stability of PLL and VCO output frequency range
4. Please consult with SEC application engineer to select the proper P, M and S values
No responsibility is assumed by SEC for its use nor for any infringements of patents or other rights of third parties that
may result from its use. The contents of the datasheet is subject to change without any notice.
FUNCTIONAL BLOCK DIAGRAM
FIN
Pre
Divider
PFD
Charge
PUMP
VCO
Post
Scaler
FOUT
Main
Divider
SAMSUNG ELECTRONICS Co. LTD

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