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PLL2060X Datasheet

  • PLL2060X

  • PLL2060X 40MHz ~ 400MHz FSPLL|Data Sheet

  • 130.76KB

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40MHz ~ 400MHz FSPLL
General Description
The PLL2060X is a Phase-Locked Loop (PLL) frequency
synthesizer constructed in CMOS process technology.
The PLL macrofunctions provide frequency multiplication
capabilities.The output clock frequency, F
OUT
, is related to
the reference input clock frequency, F
IN
, by the fllowing
equation:
F
OUT
= ((M1+2)*(M2+2)*F
IN
) / (P+2)*(2^S)
where
F
OUT
is the output clock frequency. F
IN
is the reference
input clock frequency. M1,M2,P and S are the values for
programmable dividers. PLL2060X consists of a
Phase/Frequency Detector(PFD), a Charge Pump an
External Loop Filter, a Voltage Controlled Oscillator(VCO),
a 5bit Pre-divider, a 5bit Main divider, 4bit Main divider
and 2bit Post scaler as shown in Figure 1.
PLL2060X
FEB. 2000. Ver1.11
Features
- 0.25um CMOS process technology
- 2.5V, 1.8V power supply available
- Output frequency range
40 ~ 400MHz (2.5V), 40 ~ 270MHz (1.8V)
- Jitter 鹵100ps
- Output signal duty ratio 40% to 60%
- Output frequency changed by programmable
divider ratio
- Power down mode
FUNCTIONAL BLOCK DIAGRAM
FIN
Pre Divider
P (5bit)
PFD
Charge
Pump
Loop
Filter
(Internal)
VCO
Post Scaler
FOUT
S (2bit)
F_FEED
Main Divider
M2 (5bit)
Main Divider
M1 (4bit)
FVCO
Figure 1. FUNCTIONAL BLOCK DIAGRAM
SAMSUNG ELECTRONICS Co. LTD
1/6

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