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PLL2027XA Datasheet

  • PLL2027XA

  • PLL2027XA 20MHZ~200MHZ PIXEL CLOCK GENERATOR|Data Sheet

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20MHz ~ 200MHz PIXEL CLOCK GENERATOR
General Description
The PLL2027XA is a Phase-Locked Loop (PLL) frequency
synthesizer constructed in CMOS on single monolithic
structure. The PLL macrofunctions provide frequency
multiplication capabilities.
The output clock frequency Fout is related to the reference
input clock frequency Fin by the following equation:
Fout=((M+2)*Fin)/(2
P
*2
S
)
Where, Fout is the output clock frequency.
Fin is the reference input clock frequency.
m,p and s are the values for programmable dividers.
PLL2027XA consists of a phase/Frequency Detector(PFD),
a Charge Pump an External Loop Filter, a Voltage
Controlled Oscillator(VCO), a 2bit Pre-divider, an 14bit
Main divider and 2bit Post Scaler as shown in Figure1.
PLL2027XA
Features
0.35um CMOS device technology
3.3 Volt single power supply
Input Frequency Range: 15K ~ 250KHz
Output frequency range: 20M ~ 200MHz
Clock-to-Clock Jitter 鹵150ps at 200MHz
Duty ratio 45% to 55%(All tuned range)
Frequency changed by programmable
divider
鈥?Power down mode
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
FUNCTIONAL BLOCK DIAGRAM
FIN
Pre Divider
P
PFD
Charge
Pump
VCO
Post Scaler
S
FOUT
Loop
Filter
Main Divider
M
Figure 1. Phase Locked Loop Block Diagram
Ver 2.1 (AUG. 2000 )
No responsibility is assumed by SEC for its use nor for
any infringements of patents or other rights of third parties
that may result from its use. The contents of the datasheet
is subject to change without any notice.
SAMSUNG ELECTRONICS Co. LTD

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