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PLL2026X Datasheet

  • PLL2026X

  • PLL2026X 25MHz ~ 300MHz FSPLL PLL2026X|Data Sheet

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25MHz ~ 300MHz FSPLL
General Description
The PLL2026X is a Phase-Locked Loop (PLL) frequency synthesizer
constructed in CMOS process technology. The PLL macrofunctions
PLL2026X
February 2000 V2.0
Features
鈥?/div>
0.25um CMOS process technology
鈥?/div>
2.5 Volt Single power supply
provide frequency multiplication capabilities.The output clock frequency
Fout is related to the reference input clock frequency, by the follwing
鈥?/div>
Output frequency range: 25MHz~300 MHz
equation:
Fout=( m*Fin ) / ( p*s )
where Fout is the output clock frequency. Fin is the reference input
clock frequency. m,p and s are the values for programmable dividers.
鈥?/div>
Input Duty ratio: 30% to 70%
PLL2026X consists of a Phase/Frequency Detector(PFD), a Charge
Pump an External Loop Filter, a Voltage Controlled Oscillator(VCO),
a 6bit Pre-divider, an 8bit Main divider and 2bit Post Scaler as
shown in Figure 1.
鈥?/div>
Frequency changed by programmable divider
鈥?/div>
Power down mode
鈥?/div>
Lock Detector mode
鈥?/div>
Cycle-to-cycle jitter:
鹵鈥?00ps
鈥?/div>
Output Duty ratio: 40% to 60%
FUNCTIONAL BLOCK DIAGRAM
LD
LDT
FIN
Pre Divider
P
PFD
Charge
Pump
VCO
Post Scaler
S
FOUT
FILTER
Main Divider
PWRDN
P[5]~P[0]
M[7]~M[0]
S[1],S[0]
M
AVDD25A
AVSS25A
AVDD25D
AVSS25D
AVBB25
Figure 1. Functional Block Diagram
1 / 6

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