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PLL2014X Datasheet

  • PLL2014X

  • PLL2014X 20MHZ~170MHZ FSPLL|Data Sheet

  • 12頁

  • ETC

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20MHz ~ 170MHz FSPLL
General Description
The PLL2014X is a Phase-Locked Loop (PLL)
frequency synthesizer constructed in CMOS on
single monolithic structure.
The PLL macrofunctions provide frequency
multiplication capabilities.
The output clock frequency Fout is related
to the reference input clock frequency
Fin by the following equation:
Fout = ( m*Fin ) / ( p* 2
S
)
Where,
Fout is the output clock frequency.
Fin is the reference input clock frequency.
m,p and s are the values for programmable dividers.
PLL2014X consists of a phase/Frequency Detector(PFD),
a Charge Pump an External Loop Filter, a Voltage
Controlled Oscillator(VCO), a 6bit Pre-divider,
an 8bit Main divider and 2bit Post Scaler
as shown in Figure1.
PLL2014X
DEC 98 Version1.0
Features
隆脽
0.25um CMOS device technology
隆脽
1.8 Volt Single power supply
隆脽
Output frequency range: 20~ 170 MHz
隆脽
Jitter 鹵150ps
隆脽
Duty ratio 40% to 60% at 170MHz
隆脽
Frequency changedby programmable divider
隆脽
Power down mode
FUNCTIONAL BLOCK DIAGRAM
Fin
Pre Divider
P
PFD
Charge
Pump
Loop
Filter
(External)
VCO
Fout
Post Scaler
S
Main Divider
M
Figure 1. Phase Lockd Loop Block Diagram
SAMSUNG ELECTRONICS Co. LTD

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