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PLL2013X Datasheet

  • PLL2013X

  • PLL2013X 20MHZ~170MHZ FSPLL PLL2013X|Data Sheet

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20MHz ~ 170MHz FSPLL
General Description
The PLL2013X is a Phase-Locked Loop (PLL) frequency
synthesizer constructed in CMOS on single monolithic
structure. The PLL macro-functions provide frequency
multiplication capabilities.
The output clock frequency Fout is related to the input
clock frequency Fin(XTALIN) by the following
equation:
s
Fout=(m*Fin)/(p*2 )
Where, Fout is the output clock frequency.
Fin is the input clock frequency.
m,p and s are the values for programmable dividers.
PLL2013X consists of a phase/Frequency Detector(PFD),
a Charge Pump an External Loop Filter, a Voltage
Controlled Oscillator(VCO), a 6bit Pre-divider, an 8bit
Main divider and 2bit Post Scaler as shown inFigure1.
PLL2013X
Features
0.25mm CMOS device technology
2.5 Volt single power supply
Output frequency range: 20 ~ 170 MHz
Jitter 鹵150ps at 170MHz
Duty ratio 45% to 55%(All tuned range)
Frequency changed by programmable
divider
鈥?Provision for 14.318Mhz crystal oscillator
buffer - OPTION
鈥?Power down mode
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
IMPORTANT NOTICE
- Please contact SEC application engineer to confirm the proper selection of M,P,S value.
FUNCTIONAL BLOCK DIAGRAM
FIN
Pre Divider
P
PFD
Charge
Pump
VCO
Post Scaler
S
FOUT
Loop
Filter
Main Divider
M
Figure 1. Phase Locked Loop Block Diagram
NOTE
鈥?Xtal oscillator is OPTIONAL block.
If customer concerns about this bloc k - xtal buffer or lock detector, re fer to next chapter.
Ver 2.3 ( DEC. 1999 )
No responsibility is assumed by SEC for its use nor for
any infringements of patents or other rights of third parties
that may result from its use. The contents of the datasheet
is subject to change without any notice.
SAMSUNG ELECTRONICS Co. LTD

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