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PI7C7100
3 Port PCI-to-PCI Bridge
Datasheet Brief
Product Features
聲 All three ports compliant with the
PCI Local Bus
Specification, Revision 2.1
聲 Compliant with
PCI-to-PCI Bridge Architecture Specification,
Revision 1.0
聲 32-Bit Primary and two Secondary Ports
聲 Circular-Delta Bus Architecture
聲 Concurrent primary to secondary bus operation and indepen-
dent intra-secondary port channel to reduce traffic on the
primary port
聲 Provides arbitration for two sets of 8 secondary bus masters
聳 Programmable 2-level priority arbiters
聳 Disable control for use of external arbiter
聲 Support PCI transactions for:
聳 All I/O and memory commands
聳 Type 1 to Type 0 configuration conversion
(downstream only)
聳 Type 1 to Type 1 configuration forwarding
聳 Type 1 to special cycle configuration conversion
聲 Supports posted memory write buffers in all directions
聲 Implements delayed transactions for all PCI configuration,
I/O and memory read commands
聲 Supports positive medium decoding
聲 Enhanced address decoding
聳 32-Bit I/O address range
聳 32-Bit memory-mapped I/O address range
聳 VGA addressing and VGA palette snooping
聳 ISA-aware mode for legacy support in the first 64KB of
I/O address range
聲 IEEE 1149.1 JTAG interface support
聲 Full scan support
聲 3.3V core logic with 5V tolerant 3.3V PCI signaling interface
聲 256-pin plastic PBGA package (NA256)
聲 Supports system transaction ordering rules
聲 Hot-Plug "Ready"
Product Description
Pericom聮s PI7C7100 is the first triple port PCI-to-PCI Bridge
device designed to be fully compliant with the 32-Bit, 33 MHz
implementation of the PCI Local Bus Specification, Revision 2.1.
The PI7C7100 supports synchronous bus transactions between
devices on the primary bus and the secondary buses both
operating at 33 MHz. The primary and the secondary buses can
also operate in concurrent mode, resulting in additional increase
in system performance. Concurrent bus operation offloads and
isolates unnecessary traffic from the primary bus; thereby
enabling a master and a target device on the same secondary PCI
bus to communicate even while the primary bus is busy.
Product Benefits
聲
Triple port PCI-to-PCI Bridge increases the number of PCI slots
that can be supported in a system.
聲
Single PI7C7100 device instead of two PCI-to-PCI Bridge
devices conserves board real estate and provides one less
device load on the primary bus.
聲
Concurrent and intra-secondary bus communication increases
overall system performance by reducing bus traffic on the
primary bus. Devices on secondary busses can independently
communicate while the primary bus is busy.
聲
Integrated two-level programmable arbiter support for up to 8
devices on each secondary bus maximizes master device
control. The internal arbiter can be bypassed with an external
arbiter for custom applications.
聲
Synchronous clock operation on the primary and secondary
busses
聲
Enhanced PCI bridge performance and efficiency through
support for delayed transactions.
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