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PI74FCT16511/162511T
16-BIT REGISTERED/
LATCHED TRANSCEIVER WITH PARITY
PI74FCT16511T
PI74FCT162511T
Fast CMOS 16-Bit Registered/Latched
Transceiver With Parity
Product Features
Common Features
聲 PI74FCT16511 and PI74FCT162511 are high-speed, low
power devices with high current drive.
聲 Vcc = 5V 鹵10%
聲 Typical tsk(o) (Output Skew) < 250ps, clocked mode
聲 Extended range of 聳40擄C to +85擄C
聲 Hysteresis on all inputs
聲 Packages available:
聳 56-pin 240 mil wide TSSOP (A)
聳 56-pin 300 mil wide SSOP (V)
PI74FCT16511T Features
聲 High output drive: I
OH
= 聳32mA; I
OL
= 64mA
聲 Power off disable outputs permit 聯(lián)live insertion聰
聲 Typical V
OLP
(Output Ground Bounce) < 1.0V
at V
CC
= 5V, T
A
= 25擄C
PI74FCT162511T Features
聲 High output drive: I
OL
/I
OH
= 24mA
聲 Open drain parity error allows wire-OR
聲 Typical V
OLP
(Output Ground Bounce) < 1.0V
at V
CC
= 5V, T
A
= 25擄C
聲 Balanced output drivers: 鹵24mA
聲 Series current limiting resistors
Product Description
Pericom Semiconductor聮s PI74FCT series of logic circuits are pro-
duced in the Company聮s advanced 0.8 micron CMOS technology,
achieving industry leading speed grades.
The PI74FCT16511T and PI74FCT162511T are high-speed, low-
power 16-bit registered/latched transceiver with parity which
combines D-type latches and D-type flip-flops to allow data flow in
transparent, latched or clocked modes. It has a parity generator/
checker in the A-to-B direction and a parity checker in the B-to-A
direction. Error checking is done at the byte level with separate parity
bits for each byte. One error flag for each direction (A-to-B or B-to-
A) exists to indicate an error for either byte in either direction. The
parity error flags which are open drain outputs, can be tied together
and/or tied with flags from other devices to form a single error flag
or interrupt. To disable the error flag during combinational transitions,
a designer can disable the parity error flag by the OExx control pins.
The operation in A-to-B direction is controlled by LEAB, CLKAB
and OEAB control pins, and the operation in B-to-A direction is
controlled by LEBA, CLKBA and OEBA control pins. GEN/CHK is
used to select the operation of A-to-B direction, while B-to-A
direction is always in checking mode. The ODD/EVEN select is
common between the two directions. Independent operation can be
achieved between the two directions by using the corresponding
control lines except for the ODD/EVEN control.
Simplified Logic Block Diagram
LEAB
CLKAB
Data
Parity, data
16
Parity
GEN/CHK
Byte
Parity
Generator/
Checker
2
Latch/
Register
18
B0-15
PB1,2
PERB
(Open Drain)
OEAB
A0-15
PA1,2
ODD/EVEN
LEBA
CLKBA
Parity, data
18
OEBA
PERA
(Open Drain)
Latch/
Register
Byte
Parity
Checking
Parity, data
18
1
PS2080A 01/15/95
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