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PI74AVC+16823A Datasheet

  • PI74AVC+16823A

  • 18-Bit D-Type Flip-Flop

  • 10頁(yè)

  • ETC

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V
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PI74AVC+16823
2.5V 18-Bit Bus Interface
Flip-Flop with 3-State Outputs
Product Features
鈥?/div>
PI74AVC
+
16823 is designed for low voltage operation,
V
CC
= 1.65V to 3.6V
鈥?/div>
True 鹵24mA Balanced Drive @ 3.3V
鈥?/div>
I
OFF
supports partial power-down operation
鈥?/div>
3.6V I/O Tolerant Inputs and Outputs
鈥?All outputs contain a patented DDC
(Dynamic DriveControl) circuit that reduces noise without
degrading propagation delay.
鈥?Industrial operation at 鈥?0擄C to +85擄C
鈥?Available Packages:
鈥?56-pin 240 mil wide plastic TSSOP (A)
鈥?56-pin 173 mil wide plastic TVSOP (K)
Product Description
Pericom Semiconductor鈥檚 PI74AVC
+
series of logic circuits are
produced using the Company鈥檚 advanced submicron CMOS
technology, achieving industry leading speed.
The 18-bit PI74AVC
+
16823 bus-interface flip-flop is designed for
1.65V to 3.6V V
CC
operation. It features 3-state outputs designed
specifically for driving highly capacitive or relatively low-impedance
loads. This device is particularly suitable for implementing wider
buffer registers, I/O ports, bidirectional bus drivers with parity, and
working registers.
The device can be used as two 9-bit flip-flops or one 18-bit flip-flop.
With the Clock Enable (CLKEN) input LOW, the D-type flip-flops
enter data on the low-to-high transitions of the clock. Taking
CLKEN HIGH disables the clock buffer, thus latching the outputs.
Taking the Clear (CLR) input LOW causes the Q outputs to go LOW
independently of the clock.
A buffered Output Enable (OE) input can be used to place the nine
outputs in either a normal logic state (high or low logic levels) or
high-impedance state. In the high-impedance state, the outputs
neither load n or drive the bus lines significantly. The high-
impedance state and increased drive provide the capability to drive
bus lines without need for interface or pullup components.
CE
R
C1
3
1
Q
1
Logic Block Diagram
1
OE
2
1
CLR
1
55
1
CLKEN
1
CLK
1
D
1
56
54
1D
The Output Enable (OE) input does not affect the internal operation
of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pullup resistor; the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
8
2
OE
27
2
CLR
28
30
2
CLKEN
CE
R
C1
15
2
CLK
2
D
1
29
42
2
Q
1
1D
8
1
PS8489
07/24/00

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