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PI74AVC+16821A Datasheet

  • PI74AVC+16821A

  • 2.5V 20-Bit Bus Interface Flip-Flop with 3-State Outputs

  • 518.32KB

  • 10頁

  • PERICOM   PERICOM

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21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74AVC+16821
2.5V 20-Bit Bus Interface
Flip-Flop with 3-State Outputs
Product Features
PI74AVC
+
16821 is designed for low-voltage operation,
V
CC
= 1.65V to 3.6V
True 鹵24mA Balanced Drive @ 3.3V
I
OFF
supports partial power-down operation
3.6V I/O Tolerant Inputs and Outputs
All outputs contain a patented DDC
(Dynamic Drive Control) circuit that reduces noise
without degrading propagation delay
Industrial operation: 聳40擄C to +85擄C
Available Packages:
聳 56-pin 240 mil wide plastic TSSOP (A)
聳 56-pin 173 mil wide plastic TVSOP (K)
Description
Pericom Semiconductor聮s PI74AVC+ series of logic circuits are
produced using the Company聮s advanced submicron CMOS
technology, achieving industry leading speed.
The PI74AVC+ 16821is a 20-bit bus interface flip-flop designed for
1.65V to 3.6V V
CC
operation. It can be used as two 10-bit flip-flops
or one 20-bit flip-flop. The 20 flip-flops are edge-triggered D-type
flip-flops. On the positive transition of the clock (CLK) input, the
device provides true data at the Q outputs.
A buffered output-enable (OE) input can be used to place the ten
outputs in either a normal logic state (HIGH or LOW level) or a high-
impedance state. In the high-impedance state, the outputs neither
load nor drive the bus lines significantly. The high-impedance state
and increased drive provide the capacity to drive bus lines without
the need for interface or pullup components.
OE does not affect the internal operation of the flip-flops. Old data
can be retained or new data can be entered while the outputs are in
the high-impedance state.
To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pullup resistor; the
minimum value of the resistor is determined by the current sinking
capability of the driver.
Logic Block Diagram
1
28
1
OE
2
OE
1CLK 56
One of Ten
Channels
2CLK 29
One of Ten
Channels
1
Q
1
C
1
1
D
1D
1
55
2
C
1
1
D
2D
1
42
15
2Q
1
TO 9 OTHER CHANNELS
TO 9 OTHER CHANNELS
1
PS8548
07/31/01

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