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PI74AVC+16646A Datasheet

  • PI74AVC+16646A

  • Dual 8-bit Bus Transceiver

  • 11頁

  • ETC

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PI74AVC+16646
2.5V 16-Bit Bus Transceiver and
Register with 3-State Outputs
Product Features
聲
PI74AVC
+
16646 is designed for low voltage operation,
V
CC
= 1.65V to 3.6V
聲
True 鹵24mA Balanced Drive @ 3.3V
聲
I
OFF
supports partial power-down operation
聲
3.6V I/O Tolerant Inputs and Outputs
聲 All outputs contain a patented DDC
(Dynamic DriveControl) circuit that reduces noise without
degrading propagation delay.
聲 Industrial operation at 聳40擄C to +85擄C
聲 Available Packages:
聳 56-pin 240 mil wide plastic TSSOP (A)
聳 56-pin 173 mil wide plastic TVSOP (K)
Product Description
Pericom Semiconductor聮s PI74AVC
+
series of logic circuits are
produced using the Company聮s advanced sub-micron CMOS
technology, achieving industry leading speed.
The PI74AVC
+
16646 is a 16-bit bus transceiver and register designed
for 1.65V to 3.6V V
CC
operation. It can be used as two 8-bit
transceivers or one 16-bit transceiver. Data on the A or B bus is
clocked into the registers on the low-to-high transition of the
appropriate Clock (CLKAB or CLKBA) input. Four fundamental bus-
management functions can be performed.
Output Enable (OE) and Direction Control (DIR) inputs are provided
to control the transceiver functions. In the transceiver mode, data
present at the high-impedance port may be stored in either register
or in both. The Select Control (SAB and SBA) inputs can multiplex
stored and real-time (transparent mode) data. Circuitry used for
Select Control eliminates the typical decoding glitch that occurs in
a multiplexer during the transition between stored and real-time data.
DIR determines which bus receives data when OE is LOW. In the
isolation mode (OE HIGH), A data may be stored in one register and/
or B data may be stored in the other register.
When an output function is disabled, the input function is still
enabled and may be used to store and transmit data. Only one of the
two buses, A or B, can be driven at a time.
To ensure the high-impedance state during power up or power down,
OE should be tied to V
CC
through a pullup resistor; the minimum
value of the resistor is determined by the current-sinking capability
of the driver.
Logic Block Diagrams
1OE 56
2OE 29
1DIR
1
1CLKBA 55
1SBA 54
1CLKAB
1SAB
2
3
2DIR 28
2CLKBA 30
2SBA 31
2CLKAB 27
2SAB 26
One of Eight Channels
1D
C1
One of Eight Channels
1D
C1
1A1
5
52
1D
C1
2A1
15
42
1D
C1
2B1
1B1
TO SEVEN OTHER CHANNELS
TO SEVEN OTHER CHANNELS
1
PS8506B
02/26/01

PI74AVC+16646A 產(chǎn)品屬性

  • 35

  • 集成電路 (IC)

  • 邏輯 - 緩沖器，驅(qū)動(dòng)器，接收器，收發(fā)器

  • 74AVC+

  • 寄存收發(fā)器，非反相

  • 2

  • 8

  • 24mA，24mA

  • 1.65 V ~ 3.6 V

  • -40°C ~ 85°C

  • 表面貼裝

  • 56-TFSOP（0.240"，6.10mm 寬）

  • 56-TSSOP

  • 管件

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