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PI74AVC+16268A Datasheet

  • PI74AVC+16268A

  • Bus Exchanger

  • 514.36KB

  • 11頁

  • ETC

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OEB
56
C1
V
SEL
28
1D
OEA
1
CE
V
1D
C1
V
V
V
C1
1D
V
1 of 12 Channels
1
V
V
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74AVC+16268
12-Bit to 24-Bit Registered Bus
Exchanger with 3-State Outputs
Product Features
聲
PI74AVC+16268 is designed for low-voltage operation,
V
CC
= 1.65V to 3.6V
聲
True 鹵24mA Balanced Drive @ 3.3V
聲
I
OFF
supports partial power-down operation
聲
3.6 I/O Tolerant Inputs and Outputs
聲 All outputs contain a patented DDC
(Dynamic DriveControl) circuit that reduces noise without
degrading propagation delay.
聲 Industrial operation: 聳40擄C to +85擄C
聲 Available Packages:
聳 56-pin 240 mil wide plastic TSSOP (A)
聳 56-pin 173 mil wide plastic TVSOP (K)
Product Description
Pericom Semiconductor聮s PI74AVC+ series of logic circuits are
produced using the Company聮s advanced submicron CMOS
technology, achieving industry leading speed.
The PI74AVC+16268, a 12-bit to 24-bit registered bus exchanger
designed for 1.65V to 3.6V V
CC
operation, is used for applications
in which data must be transferred from a narrow high-speed bus to
a wide, lower frequency bus. It provides synchronous data exchange
between the two ports. Data is stored in internal registers on the low-
to-high transition of the clock (CLK) input when appropriate clock-
enable (CLKEN) inputs are low. The select (SEL) line is synchronous
with CLK and selects 1B or 2B input data for the A outputs.
For data transfer in the A-to-B direction, a two-stage pipeline is
provided in the A-to-1B path, with a single storage register in the
A-to-2B path. Proper control of these inputs allows two sequential
12-bit words to be presented synchronously as a 24-bit word on the
B-port. Data flow is controlled by the active-low output enables
(OEA, OEB). These control terminals are registered so bus direction
changes are synchronous with CLK.
To ensure the high-impedance state during power up or power
down, a clock pulse should be applied as soon as possible and OE
should be tied to V
CC
through a pullup resistor, the minimum value
of the resistor is determined by the current-sinking capability of the
driver. Because OE is being routed through a register, the active
state of the outputs cannot be determined prior to the arrival of the
first clock pulse.
Logic Block Diagram
CLK
CLKEN1B
29
2
CLKEN2B 27
30
CLKENA1
CLKENA2
55
C1
1D
C1
1D
23
1
B
1
G1
1
A1
8
1
CE
C1
1D
6
2
B
1
CE
CE
C1
1D
CE
C1
1D
PS8551
07/31/01

PI74AVC+16268A 產(chǎn)品屬性

  • 35

  • 集成電路 (IC)

  • 邏輯 - 通用總線函數(shù)

  • 74AVC+

  • 寄存總線交換器

  • -

  • 12 至 24 位

  • 24mA，24mA

  • 1.65 V ~ 3.6 V

  • -40°C ~ 85°C

  • 表面貼裝

  • 56-TFSOP（0.240"，6.10mm 寬）

  • 56-TSSOP

  • 管件

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