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PI74ALVTC16841
2.5V 20-Bit Bus Interface
D-Type Latch with 3-State Outputs
Product Features
聲 PI74ALVTC16841 is designed for low voltage operation,
V
DD
= 1.65V to 3.6V
聲 Supports Live Insertion
聲 3.6V I/O Tolerant Inputs and Outputs
聲 Bus Hold
聲 High Drive, 聳32/64mA @ 3.3V
聲 Uses patented noise reduction circuitry
聲 Power-off high impedance inputs and outputs
聲 Industrial operation at 聳40擄C to +85擄C
聲 Packages available:
聳 56-pin 240-mil wide plastic TSSOP (A56)
聳 56-pin 173-mil wide plastic TVSOP (K56)
Product Description
Pericom Semiconductor聮s PI74ALVTC series of logic circuits are
produced using the Company聮s advanced 0.35 micron CMOS
technology, achieving industry leading speed.
The PI74ALVTC16841 features 3-State outputs designed specifically
for driving highly capacitive or relatively low-impedence loads. This
device is particularly suitable for implementing buffer registers,
unidirectional bus drivers, and working registers.
The device can be used as two 10-bit latches, or one 20-bit latch. The
20 latches are transparent D-type latches. The device has non-
inverting data (D) inputs and provides true data at its outputs. While
the latch-enable (1LE or 2LE) input is high, the Q outputs of the
corresponding 10-bit latch follows the D inputs. When LE is taken
low, the Q outputs are latched at the levels set up at the D inputs.
A buffered output-enable (1OE or 2OE) input can be used to place
the outputs of the corresponding 10-bit latch in either a normal logic
state (high or low logic levels) or a high-impedence state. In the high-
impedence state, the outputs neither load nor drive the bus lines
significantly.
The output enable (OE) input does not affect the internal operation
of the latches. Old data can be retained or new data or new data can
be entered while the outputs are in the high-impedence state.
To ensure the high-impedance state during power up or power down,
OE should be tied to V
DD
through a pullup resistor; the minimum
value of the resistor is determined by the current-sinking capability
of the driver.
The family offers both I/O Tolerant, which allows it to operate in
mixed 1.65/3.6V systems, and 聯(lián)Bus Hold,聰 which retains the data
input聮s last state preventing 聯(lián)floating聰 inputs and eliminating the
need for pullup/down resistors.
Logic Block Diagram
1OE
1
1LE 56
L
1D0
55
Q
D
2
1Q0
To Nine Other Channels
2OE
28
2LE 29
L
2D0 42
Q
D
15
2Q0
To Nine Other Channels
1
P0.2
04/09/02
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