ADVANCE INFORMATION
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PI74ALVTC16260
2.5V 12-Bit to 24-Bit Multiplexed
D-Type Latch with 3-State Outputs
Product Features
聲 PI74ALVTC16260 is designed for low voltage operation,
V
DD
= 1.65V to 3.6V
聲 Supports Live Insertion
聲 3.6V I/O Tolerant Inputs and Outputs
聲 Bus Hold
聲 High Drive, 聳32/64mA @ 3.3V
聲 Uses patented noise reduction circuitry
聲 Power-off high impedance inputs and outputs
聲 Industrial operation at 聳40擄C to +85擄C
聲 Packages available:
聳 56-pin 240-mil wide plastic TSSOP (A56)
聳 56-pin 173-mil wide plastic TVSOP (K56)
Product Description
Pericom Semiconductor聮s PI74ALVTC series of logic circuits are
produced using the Company聮s advanced 0.35 micron CMOS
technology, achieving industry leading speed.
The PI74ALVTC16260 is a 12-bit to 24-bit multiplexed D-type latch
designed for 1.65V to 3.6 V
DD
operation. It is used in applications
where two separate datapaths must be multiplexed onto, or
demultiplexed from, a single data path.
Typical applications include multiplexing and/or demulti-plexing
address and data information in microprocessor or bus-interface
applications. This device is also useful in memory-interleaving
applications.
Three 12-bit I/O ports (A1-A12, 1B1-1B12, and 2B1-2B12) are
available for address and/or data transfer. The output-enable
(OE1B, OE2B, and OEA) inputs control the bus transceiver functions.
The OE1B and OE2B control signals also allow bank control in the
A-to-B direction.
Address and/or data information can be stored using the internal
storage latches. The latch-enable (LE1B, LE2B, LEA1B, and LEA2B)
inputs are used to control data storage. When the latch-enable input
is HIGH, the latch is transparent. When the latch-enable input goes
LOW, the data present at the inputs is latched and remains latched
until the latch-enable input is returned HIGH.
To ensure the high-impedance state during power up or power
down, OE should be tied to V
DD
through a pullup resistor, the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
G1
C1
1
1
23
1D
1
B
1
Logic Block Diagram
LE1B
LE2B
LEA1B
LEA2B
OE2B
2
27
30
55
56
29
OE1B
1
28
OEA
SEL
A1
8
The family offers both I/O Tolerant, which allows it to operate in
mixed 1.65/3.6V systems, and 聯(lián)Bus Hold,聰 which retains the data
input聮s last state preventing 聯(lián)floating聰 inputs and eliminating the
need for pullup/down resistors.
C1
6
1D
2
B
1
C1
1D
C1
1D
TO 11 OTHER CHANNELS
1
PXXXX
04/11/00
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2
3
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7
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