鈥?/div>
Packages available:
聳 56-pin 240 mil wide plastic TSSOP (A)
聳 56-pin 300 mil wide plastic SSOP (V)
Product Description
Pericom Semiconductor鈥檚 PI74ALVCH series of logic circuits are
produced in the Company鈥檚 advanced 0.5 micron CMOS technology,
achieving industry leading speed.
The PI7ALVCHR16269 is used in applications in which two separate
ports must be multiplexed onto, or demultiplexed from, a single port.
It is particularly suitable as an interface between synchronous DRAM鈥檚
and high-speed microprocessors.
Data is stored on the internal B-port registers on the low-to-high
transition of the clock (CLK) input when the appropriate clock-enable
(CLKENA) inputs are low. Proper control of these inputs allows two
sequential 12-bit words to be presented as a 24-bit word on the B-port.
For data transfer in the B-to-A direction, a single storage register is
provided. The select (SEL) line selects 1B or 2B data for the A outputs.
The register on the A output permits the fastest possible data transfer,
thus extending the period during which the data is valid on the bus. The
control terminals are registered so that all transactions are synchronous
with CLK. Data flow is controlled by the active-low output enables
(OEA, OEB1, and OEB2).
To ensure the high-impedance state during power up or power
down, a clock pulse should be applied as soon as possible and OE
should be tied to V
CC
through a pullup resistor; the minimum value
of the resistor is determined by the current-sinking capability of the
driver. Due to OE being routed through a register, the active state
of the outputs cannot be determined prior to the arrival of the first
clock pulse.
Active bus-hold circuitry is provided to hold unused or floating
data inputs at a valid logic level.
All outputs are designed to sink up to 12mA and include 26鈩?/div>
resistors to reduce overshoot and undershoot.
Logic Block Diagram
1
PS8372
01/28/99
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