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PI74ALVCH32373 Datasheet

  • PI74ALVCH32373

  • Logic | 32-Bit Transparent D-Type Latch with 3-State Outputs

  • 7頁

  • ETC

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PI74ALVCH32373
32-Bit Transparent D-Type Latch
with 3-State Outputs
Product Features
鈥?/div>
PI74ALVCH32373 is designed for low voltage operation
鈥?/div>
V
CC
= 2.3V to 3.6V
鈥?/div>
Typical V
OLP
(Output Ground Bounce)
< 0.8V at V
CC
= 3.3V, T
A
= 25擄C
鈥?/div>
Typical V
OHV
(Output V
OH
Undershoot)
> 2.0V at V
CC
= 3.3V, T
A
= 25擄C
鈥?/div>
Bus Hold retains last active bus state during 3-State,
eliminating the need for external pullup resistors
鈥?/div>
Industrial operation at 聳40擄C to +85擄C
鈥?/div>
Packages available:
聳 96-ball, 13.5mm x 5.5mm x 1.4mm low profile fine
pitch ball grid array, LFBGA (NB)
Product Description
Pericom Semiconductor聮s PI74ALVCH series of logic circuits are
produced using the Company聮s advanced 0.5 micron CMOS
technology, achieving industry leading speed.
This 32-bit transparent D-type latch is designed for 2.3V to 3.6V V
CC
operation.
The PI74ALVCH32373 is particularly suitable for implementing
buffer registers, I/O ports, bidirectional bus drivers, and working
registers. This device can be used as four 8-bit latches or two 16-
bit latches or one 32-Bit latch. When the Latch Enable (LE) input
is HIGH, the Q outputs follow the (D) inputs. When LE is taken
LOW, the Q outputs are latched at the levels set up at the D inputs.
A buffered Output Enable (OE) input can be used to place the
eight outputs in either a normal logic state (high or low logic
levels) or a high-impedance state in which the outputs neither
load nor drive the bus lines significantly. The high-impedance state
and the increased drive provide the capability to drive bus lines
without need for interface or pullup components. OE does not
affect internal operations of the latch. Old data can be retained
or new data can be entered while the outputs are in the high
impedance state.
To ensure the high impedance state during power up or power
down, OE should be tied to V
CC
through a pullup resistor; the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating
data inputs at a valid logic level.
Product Pin Description
Pin Name
OE
LE
Dx
Qx
GND
V
CC
Description
Output Enable Input (Active LOW)
Latch Enable (Active HIGH)
Data Inputs
3-State Outputs
Ground
Power
Truth Table
(1)
Inputs
OE
L
L
L
H
LE
H
H
L
X
D
H
L
X
X
Outputs
Q
H
L
Q
0
Z
Notes:
1. H = High Signal Level
L = Low Signal Level
X = Irrelevant
Z = High Impedance
1
PS8438
10/14/99

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