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PI74ALVCH16825V Datasheet

  • PI74ALVCH16825V

  • 9-Bit Buffer/Driver

  • 4頁(yè)

  • ETC

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PI74ALVCH16825
3.3V 18-Bit Buffer/Driver
with 3-State Outputs
Product Features
鈥?/div>
PI74ALVCH16825 is designed for low-voltage operation
鈥?/div>
V
CC
= 2.3V to 3.6V
鈥?/div>
Hysteresis on all inputs
鈥?/div>
Typical V
OLP
(Output Ground Bounce)
< 0.8V at V
CC
= 3.3V, T
A
= 25擄C
鈥?/div>
Typical V
OHV
(Output V
OH
Undershoot)
< 2.0V at V
CC
= 3.3V, T
A
= 25擄C
鈥?/div>
Bus Hold retains last active bus state during 3-State,
eliminating the need for external pullup resistors
鈥?/div>
Industrial operation at 聳40擄C to +85擄C
鈥?/div>
Packages available:
聳 56-pin 240 mil wide plastic TSSOP (A)
聳 56-pin 300 mil wide plastic SSOP (V)
Product Description
Pericom Semiconductor聮s PI74ALVCH series of logic circuits are
produced using the Company聮s advanced 0.5 micron CMOS
technology, achieving industry leading speed.
This 18-bit buffer and line driver is designed for 2.3V to 3.6V V
CC
operation.
PI74ALVCH16825 improves the performance and density of 3-
state memory address drivers, clock drivers, and bus-oriented
receivers and transmitters.
Providing true data, the device can be used as two 9-bit buffers or
one 18-bit buffer.
The 3-state control gate is a 2-input AND gate with Active-Low
inputs so that if either Output Enable (OE1 or OE2) input is HIGH,
all nine affected outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power
down, OE should be tied to Vcc through a pull-up resistor; the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating
inputs at a valid logic level.
Logic Block Diagram
1
OE
1
1
OE
2
1
56
2
OE
1
2
OE
2
28
29
1
A
1
55
2
1
Y
1
2
A
1
41
16
2
Y
1
To Eight Other Channels
To Eight Other Channels
1
PS8158
11/17/97

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