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PI74ALVCH16646 is designed for low voltage operation
V
CC
= 2.3V to 3.6V
Hysteresis on all inputs
Typical V
OLP
(Output Ground Bounce)
< 0.8V at V
CC
= 3.3V, T
A
= 25擄C
Typical V
OHV
(Output V
OH
Undershoot)
< 2.0V at V
CC
= 3.3V, T
A
= 25擄C
Bus Hold retains last active bus state during 3-STATE,
eliminating the need for external pullup resistors
Industrial operation at 聳40擄C to +85擄C
Packages available:
聳 56-pin 240 mil wide plastic TSSOP (A)
聳 56-pin 300 mil wide plastic SSOP (V)
Product Description
16-Bit Bus Transceiver and Register
with 3-STATE Outputs
Pericom Semiconductor聮s PI74ALVCH series of logic circuits are
produced in the Company聮s advanced 0.5 micron CMOS
technology, achieving industry leading speed.
The PI74ALVCH16646 is a 16-bit bus transceiver and register
designed for 2.3V to 3.6V V
CC
operation. It can be used as two
8-bit transceivers or one 16-bit transceiver. Data on the A or B bus
is clocked into the registers on the low-to-high transition of the
appropriate Clock (CLKAB or CLKBA) input. Four fundamental
bus-management functions can be performed.
Output Enable (OE) and Direction Control (DIR) inputs are provided
to control the transceiver functions. In the transceiver mode, data
present at the high-impedance port may be stored in either register
or in both. The Select Control (SAB and SBA) inputs can multiplex
stored and real-time (transparent mode) data. Circuitry used for
Select Control eliminates the typical decoding glitch that occurs in
a multiplexer during the transition between stored and real-time
data. DIR determines which bus receives data when OE is LOW.
In the isolation mode (OE HIGH), A data may be stored in one
register and/or B data may be stored in the other register.
When an output function is disabled, the input function is still
enabled and may be used to store and transmit data. Only one of the
two buses, A or B, can be driven at a time.
To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pullup resistor; the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
Logic Block Diagram
Active bus-hold circuitry is provided to hold unused or floating
data inputs at a valid logic level.
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