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PI74ALVCH16543 is designed for low voltage operation
V
CC
= 2.3V to 3.6V
Hysteresis on all inputs
Typical V
OLP
(Output Ground Bounce)
< 0.8V at V
CC
= 3.3V, T
A
= 25擄C
Typical V
OHV
(Output V
OH
Undershoot)
< 2.0V at V
CC
= 3.3V, T
A
= 25擄C
Bus Hold retains last active bus state during 3-State,
eliminating the need for external pullup resistors
Industrial operation at 聳40擄C to +85擄C
Packages available:
聳 56-pin 240 mil wide plastic TSSOP (A)
聳 56-pin 300 mil wide plastic SSOP (V)
Product Description
Pericom Semiconductor聮s PI74ALVCH series of logic circuits are
produced in the Company聮s advanced 0.5 micron CMOS technology,
achieving industry leading speed.
The PI74ALVCH16543, a 16-bit registered transceiver designed
for 2.3V to 3.6V V
CC
operation, can be used as two 8-bit transceivers
or one 16-bit transceiver. Separate Latch Enable (LEAB or LEBA),
and Output Enable (OEAB and OEBA) inputs are provided for each
register to permit independent control in either direction of data
flow.
The A-to-B Enable (CEAB) input must be LOW to enter data from
A or to output data from B. If CEAB is LOW and LEAB is LOW,
the A-to-B latches are transparent; a subsequent low-to-high
transition of LEAB puts the A latches in the storage mode. With
CEAB and OEAB both LOW, the 3-State B outputs are active and
reflect the data present at the output of the A latches. Data flow from
B to A is similar but requires using CEBA, LEBA, and OEBA.
To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pull-up resistor; the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating
data inputs at a valid logic level.
Logic Block Diagram
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PS8128A 11/06/00
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