TO 19 OTHER CHANNELS
V
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PI74ALVC162836
20-Bit Universal Bus Driver
with 3-State Outputs
Product Features
聲 PI74ALVC162836 is designed for low-voltage operation,
V
CC
= 2.3V to 3.6V
聲 Supports PC100 Registered DIMM
聲 Typical V
OLP
(Output Ground Bounce)
< 0.8V at V
CC
= 3.3V, T
A
= 25擄C
聲 Typical V
OHV
(Output V
OH
Undershoot)
< 2.0V at V
CC
= 3.3V, T
A
= 25擄C
聲 Outputs have equivalent 26-ohm series resistors
聲 Industrial operation at 聳40擄C to +85擄C
聲 Packages available:
聳 56-pin 240 mil wide plastic TSSOP (A)
聳 56-pin 173 mil wide plastic TVSOP (K)
聳 56-pin 300 mil wide plastic SSOP (V)
Product Description
Pericom Semiconductor聮s PI74ALVC series of logic circuits are
produced using the Company聮s advanced submicron CMOS
technology, achieving industry leading speed.
The 20-bit PI74ALVC162836 universal bus driver is designed
for 2.3V to 3.6V V
CC
operation.
Data flow from A to Y is controlled by the Output Enable (OE) input.
The device operates in the transparent mode when the latch-enable
(LE) input is LOW. When LE is HIGH, the A data is latched if the clock
(CLK) input is held at a high or low logic level. If LE is HIGH, the A
data is stored in the latch/flip-flop on the low-to-high transition of
CLK. When OE is HIGH , the outputs are in the high-impedance state,
but all the inputs are enabled and data is capable of being stored in
the register.
To ensure the high-impedance state during power up or power down,
OE should be tied to V
CC
through a pullup resistor; the minimum
value of the resistor is determined by the current-sinking capability
of the driver.
Logic Block Diagram
OE
1
Product Pin Description
Pin Name
OE
LE
CLK
A
Y
GND
V
CC
1D
C1
CLK
Description
Output Enable Input (Active LOW)
Latch Enable (Active LOW)
Clock Input
Data Input
Data Output
Ground
Power
CLK
LE
56
29
A1 55
2
Y1
1
PS8204A
04/06/01
1
2
3
4
5
