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PI6C9930Q Datasheet

  • PI6C9930Q

  • Eight Distributed-Output Clock Driver

  • 5頁

  • ETC

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PI6C9930
3.3V Zero-Delay Clock Buffer
Features
鈥?/div>
Near zero input to output delay
鈥?/div>
Seven copies of the REF/2 or
Six copies of REF plus one REF 脳 2
鈥?/div>
25 聳 100 MHz output
鈥?/div>
50% duty cycle
鈥?/div>
Low skew
鈥?/div>
Low jitter (<250ps cycle-to-cycle)
鈥?/div>
Low noise balanced drive outputs
鈥?/div>
V
CC
= 3.3V 鹵0.3V, T
A
= 0擄 to 70擄
鈥?/div>
24-pin 209 mil wide SSOP (H)
鈥?/div>
24-pin 150 mil wide QSOP (Q)
鈥?/div>
24-pin 300 mil wide SOIC (S)
Product Description
The PI6C9930 Clock Buffer offers zero-delay, low-skew system
clock distribution. These multiple output clock drivers optimize the
timing of high-performance computer systems. Each of eight
individual drivers can drive series-terminated transmission lines
with impedances as low as 50鈩?while delivering minimal output
skews and full-swing logic levels.
Connecting Q0 to FB provides REF/2 outputs on Q1-Q7. Connecting
any of Q1 - Q7 output to FB produces six copies of the REF input
plus one REF x 2 on Q0.
Test Mode
In normal system operation, this pin is connected to ground. For
testing purposes, the TEST pin can have a removable jumper to
ground, or be tied LOW through a 100鈩?resistor. This will allow drive
by an external tester. If the TEST input is forced HIGH, the device
will operate with its internal phase-locked loop disconnected, and
input levels supplied to REF will directly control all outputs.
Relative output to output functions are the same as in normal mode.
Applications
鈥?/div>
PCI 66 MHz or 33 MHz systems
Block Diagram
Pinout
24-Pin
H, Q, S
177
PS8096B
01/25/99

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