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PI6C3991JI Datasheet

  • PI6C3991JI

  • Eight Distributed-Output Clock Driver

  • 449.08KB

  • 12頁

  • ETC

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FB
REF
Phase
Freq.
DET
FS
4F0
4F1
Filter
VCO and
Time Unit
Generator
4Q0
3F1
4F0
4F1
V
CCQ
V
CCN
4Q1
4Q0
GND
GND
3F0
FS
V
CCQ
REF
GND
TEST
2F1
4
5
6
7
8
9
10
11
12
13
14 15 16 17 18 19
20
3
2
1
32 31
30
29
28
27
3Q1
3Q0
V
CCN
1F0
1F1
1Q0
1Q1
1
V
CCN
2Q1
2Q0
FB
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C3991
3.3V High Speed Low-Voltage
Programmable Skew Clock Buffer
SuperClock
TM
Features
聲 All output pair skew <100ps typical (250 Max.)
聲 3.75 MHz to 80 MHz output operation
聲 User-selectable output functions
聴 Selectable skew to 18ns
聴 Inverted and Non-Inverted
聴 Operation at 錕?frac12; and 錄 input frequency
聴 Operation at 2X and 4X input frequency
(input as low as 3.75 MHz)
聲 Zero input-to-output delay
聲 50% duty-cycle outputs
聲 LVTTL outputs drive 50 Ohm terminated lines
聲 Operates from a single 3.3V supply
聲 Low operating current
聲 Available in 32-pin PLCC (J) package
聲 Jitter < 200ps peak-to-peak (< 25ps RMS)
Description
The PI6C3991 offers selectable control over system clock functions.
These multiple-output clock drivers provide the system integrator
with functions necessary to optimize the timing of high-performance
computer systems. Eight individual drivers, arranged as four pairs
of user-controllable outputs, can each drive terminated transmission
lines with impedances as low as 50 Ohm while delivering minimal and
specified output skews and full-swing logic levels (LVTTL).
Each output can be hardwired to one of nine delay or function
configurations. Delay increments of 0.7ns to 1.5ns are determined by
the operating frequency with outputs able to skew up to 鹵6 time units
from their nominal 聯(lián)zero聰 skew position. The completely integrated
PLL allows external load and transmission line delay effects to be
canceled. The user can create output-to-output delays of up to 鹵12
time units.
Divide-by-two and divide-by-four output functions are provided for
additional flexibility in designing complex clock systems. When
combined with the internal PLL, these divide functions allow distri-
bution of a low-frequency clock that can be multiplied by two or four
at the clock destination. This facility minimizes clock distribution
difficulty while allowing maximum system user-clock speed and
flexibility.
Logic Block Diagram
Test
Pin Configuration
Select Inputs
(three level)
4Q1
Skew
Select
Matrix
3Q0
3Q1
2Q0
2Q1
3F0
3F1
2F0
2F1
32-Pin
J
26
25
24
23
22
21
2F0
GND
1F1
1F0
V
CCN
1Q0
1Q1
GND
GND
PS8450
01/27/00

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