音影先锋亚洲天堂网|电影世界尽头的爱完整版播放|国产 熟女 91|高清无码免费观看欧美日韩|韩国一区二区三区黄色录像|美女亚洲加勒比在线|亚洲综合网 开心五月|7x成人在线入口|成人网站免费日韩毛片区|国产黄片?一级?二级?三级

PI6C2510-133 Datasheet

  • PI6C2510-133

  • Low-Noise, Phase-Locked Loop Clock Driver with 10 Clock Outp...

  • 142.55KB

  • 5頁

  • PERICOM   PERICOM

掃碼查看芯片數(shù)據(jù)手冊

上傳產(chǎn)品規(guī)格書

PDF預(yù)覽

21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C2510-133
Low-Noise, Phase-Locked Loop
Clock Driver with 10 Clock Outputs
Features
鈥?/div>
鈥?/div>
Description
The PI6C2510-133 is a 鈥渜uiet,鈥?low-skew, low-jitter, phase-locked
loop (PLL) clock driver, distributing high-frequency clock signals
for SDRAM and server applications. By connecting the feedback
FB_OUT output to the feedback FB_IN input, the propagation
delay from the CLK_IN input to any clock output will be nearly zero.
This zero-delay feature allows the CLK_IN input clock to be
distributed, providing one clock input to one bank of ten outputs,
with an output enable.
This clock driver is designed to meet the PC133 SDRAM Registered
DIMM specification. For test purposes, the PLL can be bypassed
by strapping AV
CC
to ground.
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Operating Frequency up to 150 MHz
Low-Noise Phase-Locked Loop Clock Distribution that
meets 133 MHz Registered DIMM Synchronous DRAM
modules for server/workstation/PC applications
Allows Clock Input to have Spread Spectrum modulation
for EMI reduction
Zero Input-to-Output delay: Distribute one Clock Input
to one Bank of Ten outputs, with an output enable.
Low jitter: Cycle-to-Cycle jitter 鹵75ps max.
On-chip series damping resistor at clock output drivers
for low noise and EMI reduction
Operates at 3.3V V
CC
Packaging(Pb-free & Green available):
- 24-pin TSSOP (L)
Block Diagram
Pin Configuration
AGND
V
CC
Y0
Y1
Y2
GND
GND
Y3
Y4
V
CC
G
FB_OUT
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
CLK_IN
AV
CC
V
CC
Y9
Y8
GND
GND
Y7
Y6
Y5
V
CC
FB_IN
G
10
Y[0:9]
FB_OUT
CLK_IN
FB_IN
AVcc
PLL
24-Pin
L
Functional Table
Inputs
G
L
H
Outputs
Y[0:9]
L
CLK_IN
FB_OUT
CLK_IN
CLK_IN
1
PS8383B
09/14/04

PI6C2510-133相關(guān)型號(hào)PDF文件下載

  • 型號(hào)
    版本
    描述
    廠商
    下載
  • 英文版
    Clock IC | 100 MHz Dual Pentium II Desktop Clock
    ETC
  • 英文版
    Clock IC | 100 MHz Dual Pentium II Desktop Clock
  • 英文版
    Precision Clock Synthesizer for Mobile PCs
    PERICOM
  • 英文版
    Precision Clock Synthesizer for Mobile PCs
    PERICOM [P...
  • 英文版
    Precision Clock Synthesizer
    PERICOM
  • 英文版
    Precision Clock Synthesizer
    PERICOM [P...
  • 英文版
    Spread Spectrum Clock Synthesizer for Desktop Pentium II
    PERICOM
  • 英文版
    Spread Spectrum Clock Synthesizer for Desktop Pentium II
    PERICOM [P...
  • 英文版
    Precision Clock Synthesizer for Mobile PCs
    Pericom Semicon...
  • 英文版
    Pentium/Pro System Clock Chip
    PERICOM
  • 英文版
    Pentium/Pro System Clock Chip
    PERICOM [P...
  • 英文版
    Clock IC | Desktop PC. 18 Output Clock Driver
    ETC
  • 英文版
    Clock IC | Desktop PC. 18 Output Clock Driver
  • 英文版
    Clock IC | Mobile PC. 10 Output Clock Driver
    ETC
  • 英文版
    Clock IC | Desktop PC. 13 Output Clock Driver (IMI compatibl...
    ETC
  • 英文版
    3.3V PRECISION CLOCK GENERATOR
    PERICOM
  • 英文版
    3.3V PRECISION CLOCK GENERATOR
    PERICOM [P...
  • 英文版
    3.3V PRECISION CLOCK GENERATOR
    PERICOM
  • 英文版
    3.3V PRECISION CLOCK GENERATOR
    PERICOM [P...
  • 英文版
    Clock IC | 750ps Accuracy. 5V. TTL. 3.75 to 80 MHz
    ETC

掃碼下載APP，
一鍵連接廣大的電子世界。

在線人工客服

買家服務(wù)：
賣家服務(wù)：
技術(shù)客服：

0571-85317607

網(wǎng)站技術(shù)支持

13606545031

客服在線時(shí)間周一至周五
9:00-17:30

關(guān)注官方微信號(hào)，
第一時(shí)間獲取資訊。

建議反饋

聯(lián)系人：

聯(lián)系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫提出的寶貴意見，您的參與是維庫提升服務(wù)的動(dòng)力！意見一經(jīng)采納，將有感恩紅包奉上哦！