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PI6C2504AQ Datasheet

  • PI6C2504AQ

  • Phase-Locked Loop Clock Driver with 4 Clock Outputs

  • 4頁

  • PERICOM   PERICOM

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PI6C2504A
Phase-Locked Loop Clock Driver
with 4 Clock Outputs
Product Features
鈥?/div>
High-Performance Phase-Locked-Loop Clock
Distribution for Networking
鈥?/div>
Registered DIMM Synchronous DRAM modules
for server/workstation/PC applications
鈥?/div>
Allows Clock Input to have Spread Spectrum
modulation for EMI reduction
鈥?/div>
Zero Input-to-Output delay
鈥?/div>
Low jitter: Cycle-to-Cycle jitter 鹵75ps max.
鈥?/div>
On-chip series damping resistor at clock output
drivers for low noise and EMI reduction
鈥?/div>
Operates at 3.3V V
CC
鈥?/div>
Wide range of Clock Frequencies 80 to 134 MHz
鈥?/div>
Package: Plastic 16-pin QSOP Package (Q)
Product Description
The PI6C2504A features a low-skew, low-jitter, phase-locked loop
(PLL) clock driver, distributing high-frequency clock signals for
SDRAM and server applications. By connecting the feedback
FB_OUT output to the feedback FB_IN input, the propagation
delay from the CLK_IN input to any clock output will be nearly zero.
Logic Block Diagram
G
4
PLL
FB_IN
AVCC
FB_OUT
Y[0:3]
Product Pin Configuration
AGND
VCC
Y0
Y1
GND
1
2
3
4
5
6
7
8
16
15
14
CLK_IN
AVCC
GND
GND
Y3
Y2
VCC
FB_IN
CLK_IN
16-Pin
Q
13
12
11
10
9
Functional Table
Inputs
G
L
H
Y[0:3]
L
CLK _IN
Outputs
FB_O UT
CLK _IN
CLK _IN
VCC
G
FB_OUT
1
PS8501
10/02/00

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