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Package: Plastic 8-pin SOIC (W)
Product Description
The PI6C2501 features a low-skew, low-jitter, phase-locked loop
(PLL) clock driver. By connecting the CLK_OUT output to the
feedback FB_IN input, the propagation delay from the CLK_IN
input to CLK_OUT output will be nearly zero.
Application
If a system designer needs more than 16 outputs with the features
just described, using two or more zero-delay buffers, such as the
PI6C2509Q, or PI6C2510Q, is likely to be impractical. The
device-to-device skew introduced can significantly reduce the
performance. Pericom recommends using a zero-delay buffer and
an eighteen output non-zero-delay buffer. As shown in Figure 1,
this combination produces a zero-delay buffer with all the signal
characteristics of the original zero-delay buffer, but with as many
outputs as the non-zero-delay buffer part. For example, when
combined with an eighteen output non-zero delay buffer, a system
designer can create a seventeen-output zero-delay buffer.
Logic Block Diagram
Product Pin Configuration
AGND
GND
CLK_OUT
VCC
1
2
3
4
8
CLK_IN
AVCC
GND
FB_IN
CLK_IN
PLL
FB_IN
AV
CC
CLK_OUT
8-Pin
W
7
6
5
Feedback
C
Reference
Clock
Signal
Zero Delay
Buffer
PI6C2501
CLK_OUT
18 Outputs
Non-PLL
Buffer
17
Figure 1. This Combination Provides Zero-Delay Between
the Reference Clock Signal and 17 Outputs
1
PS8381A
07/17/00
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