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PI6C2309-1WI Datasheet

  • PI6C2309-1WI

  • Nine Distributed-Output Clock Driver

  • 575.64KB

  • 9頁

  • ETC

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PI6C2305/PI6C2309
Zero-Delay Clock Buffer
Product Features
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Maximum rated frequency: 133 MHz
Low cycle-to-cycle jitter
Input to output delay, less than 200ps
Internal feedback allows outputs to be synchronized
to the clock input
鈥?/div>
5V tolerant input*
鈥?/div>
Operates at 3.3V V
DD
鈥?/div>
Space-saving Packages:
150-mil SOIC (W)
173-mil TSSOP (L)
* FB_IN and CLKIN must reference the same voltage thresh-
olds for the PLL to deliver zero delay skewing
Functional Description
The PI6C230x is a PLL based, zero-delay buffer, with the ability
to distribute five outputs on PI6C2305, nine outputs on PI6C2309 of
up to 133MHz at 3.3V. All the outputs are distributed from a single
clock input CLKIN and output CLK0 performs zero delay by connect-
ing a feedback to PLL.
PI6C2309 has two banks of four outputs that can be controlled by
the selection inputs, SEL1 & SEL2. It also has a powersparing feature:
when input SEL1 is 0 and SEL2 is 1, PLL is turned off and all
outputs are referenced from CLKIN. PI6C2305 is an 8-pin version
of PI6C2309 without selection inputs. PI6C230X is available in
high drive and industrial environment versions.
An internal feedback on OUT0 is used to synchronize the outputs
to the input; the relationship between loading of this signal
and the outputs determines the input-output delay.
PI6C230X are characterized for both commercial and industrial
operation
Block Diagram: PI6C2309
OUT0
CLKIN
PLL
MUX
OUTA1
OUTA2
OUTA3
SEL1
SEL2
Decode
Logic
OUTA4
OUTB1
OUTB2
PI6C2309 (-1, -1H)
OUTB3
OUTB4
Notice:
This device is subject to import restriction. Please refer
Pin Configuration PI6C2309
CLKIN
OUTA1
OUTA2
VDD
GND
OUTB1
OUTB2
SEL2
16
1
15
2
14
3
16-Pin
13
4
W, L
12
5
11
6
10
7
9
8
OUT0
OUTA4
OUTA3
VDD
GND
OUTB4
OUTB3
SEL1
to the Import Restriction Notice under the Ordering Information
section.
Block Diagram: PI6C2305
Pin Configuration: PI6C2305
CLKIN
1
2
3
4
8
CLK0
CLK4
V
DD
CLK3
CLKIN
PLL
OUT0
OUT1
OUT2
OUT3
CLK2
CLK1
GND
8-Pin
W, L
7
6
5
PI6C2305(鈥?, 鈥?H)
OUT4
1
PS8478B
10/30/01

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