鈥?/div>
Wide range of Clock Frequencies
Product Description
The PI6C2301 features a low-skew, low-jitter, phase-locked loop
(PLL) clock driver. By connecting the feedback CLK_OUT output
to the feedback FB_IN input, the propagation delay from the
CLK_IN input to any clock output will be nearly zero.
Application
If the system designer needs more than 16 outputs with the features
just described, using two or more zero-delay buffers such as
PI6C2509Q, and PI6C2510Q, is likely to be impractical. The
device-to-device skew introduced can significantly reduce
the performance. Pericom recommends the use of a zero-delay
buffer and an eighteen output non-zero-delay buffer . As shown in
Figure 1, this combination produces a zero-delay buffer with all the
signal characteristics of the original zero-delay buffer, but with as
many outputs as the non-zero-delay buffer part. For example, when
combined with an eighteen output non-zero delay buffer, a system
designer can create a seventeen-output zero-delay buffer.
Notice:
This device is subject to import restriction. Please refer
Logic Block Diagram
to the Import Restriction Notice under the Ordering Information
section.
Product Pin Configuration
CLK_IN
FB_IN
S
PLL
CLK_OUT
CLK_IN
AV
CC
AGND
CLK_OUT
1
2
3
4
8-Pin
W
8
7
6
5
FB_IN
V
CC
GND
S
Feedback
Control Input
S
Zero Delay
CLK_OUT
Buffer
PI6C2301
18 Output
Non-Zero
Delay
Buffer
Output Source
PLL
CLK_IN
PLL Shutdown
N
Y
1
17
0
Reference
Clock
Signal
Figure 1. This Combination Provides Zero-Delay Between
the Reference Clocks Signal and 17 Outputs
1
PS8419A
12/07/01
1
2
3
4
