21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C210
Differential Clock Generator
Features
聲 Eight copies of Differential CPU Clock Output at 100 MHz
聲 One copy of CLK33
聲 One copy of 14.31818 MHz Reference Clock
聲 One copy of Differential 48 MHz Clock
聲 External Resistor for Current Reference
聲 Selection Logic for Differential Swing Control, Test Mode,
HI-Z, Power-Down, Spread Spectrum
聲 Available Packaging:
聳 48-pin TSSOP (A package)
聳 48-pin SSOP (V package)
Description
Pericom聮s PI6C210 is produced using the Company聮s advanced
submicron technology.
The clocks for the CPU are provided by HCLK and HCLK_bar
[0:7] outputs. These eight differential CPU clock pairs run at 100
MHz. The V
OH
swing amplitude is configured by the MultSel0
and MultSel1 pins.
Pin Configuration
CLK33
VDD
48 MHz/SELA
48 MHz_bar/SELB
GND
VDD
HCLK0
HCLK0_bar
GND
HCLK1
HCLK1_bar
VDD
HCLK2
HCLK2_bar
GND
HCLK3
HCLK3_bar
VDD
REFCLK
SPREAD#
VSS
XTALI
XTALO
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
SEL100/133
GND
VDDA
GNDA
PWRDN#
VDD
HCLK4
HCLK4_bar
GND
HCLK5
HCLK5_bar
VDD
HCLK6
HCLK6_bar
GND
HCLK7
HCLK7_bar
VDD
MULTSEL0
MULTSEL1
GND
GNDA
IREF
VDDA
Block Diagram
XTAL_IN
XTAL_OUT
REF
OSC
1
REFCLK
48-pin
A, V
Spread#
MultSel0
MultSel1
PWRDWN#
Sel100/133
SelA
SelB
PLL2
Control
Register
/3, /4, /6
PLL1
8
HCLK [0:7]
8
HCLK_bar [0:7]
1
CLK33
1
48 MHz
1
48 MHz_bar
1
PS8599
01/29/02