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PI6C184BH Datasheet

  • PI6C184BH

  • THIRTEEN DISTRIBUTED-OUTPUT CLOCK DRIVER|CMOS|SSOP|28PIN|PLA...

  • 7頁

  • ETC

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PI6C184B
Precision 1-13 Clock Buffer
Product Features
鈥?/div>
High speed, to 133 MHz
鈥?/div>
Low noise non-inverting 1-13 buffer
鈥?/div>
Supports up to four SDRAM DIMMs
鈥?/div>
Low skew (< 250ps) between any two output clocks
鈥?/div>
I
2
C Serial Configuration interface
鈥?/div>
Multiple V
DD
, V
SS
pins for noise reduction
鈥?/div>
3.3V power supply voltage
鈥?/div>
Separate Hi-Z pin for testing
鈥?/div>
Package: 28-pin SSOP packages (H)
Description
The PI6C184B, a high-speed low-noise 1-13 non-inverting buffer
designed for SDRAM clock buffer applications, is intended to be
used with the PI6C104 clock generator for Intel Architecture for both
desktop and mobile systems.
At power up, all SDRAM outputs are enabled and active. The I
2
C
Serial control may be used to individually activate/deactivate any
of the 13 output drivers.
Note:
Purchase of I
2
C components from Pericom conveys a license to
use them in an I
2
C system as defined by Philips.
Block Diagram
Pin Configuration
SDRAM0
Vdd
SDRAM1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28-Pin
H
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vdd
SDRAM11
SDRAM10
Vss
Vdd
SDRAM9
SDRAM8
Vss
Vdd
SDRAM7
SDRAM6
Vss
Vss
SCLK
SDRAM0
SDRAM1
Vss
BUF_IN
SDRAM2
Vdd
SDRAM2
SDRAM3
Vss
BUF_IN
SDRAM4
SDRAM5
SDRAM12
Vdd
SDATA
SDRAM3
SDRAM12
SDATA
2
I C
I/O
SCLOCK
1
PS8467
05/03/00

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