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PI6C133-03V Datasheet

  • PI6C133-03V

  • CPU System Clock Generator

  • 15頁

  • ETC

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PI6C133-03
133 MHz Clock Generation
for Pentium II/III Processors
Features
聲 Four copies of CPU Clock @ 133/100 MHz
聲 Eight copies of PCI Clock (Synchronous w/CPU Clock)
including one free running PCI clock.
聲 Two copies of fixed frequencies 3.3V Clock @ 66 MHz
聲 Three copies of APIC Clock @ 16.667 MHz,
synchronous to CPU Clock
聲 One copy of 48 MHz Clock
聲 Two copies of Ref. Clock @ 14.13818 MHz
聲 Ref.14.31818 MHz Xtal Oscillator Input
聲 CPU Clock Frequency selection pin for selecting
133 MHz or 100 MHz operation
聲 Power Management Control Input Pins
聲 Supports Reliance (RCC) chip set
聲 Spread Spectrum enable/disable pin
聲 56-pin SSOP (V) package
Description
The PI6C133, a low-skew, low-jitter 133 MHz clock generator,
is specifically designed to meet all the clocking requirements for
133 MHz and 100 MHz desktops with high-performance and
lower-power features.
Split power supplies of 2.5V and 3.3V are used to reduce power
consumption, minimize noise and to ensure CPU independence.
The 2.5V supply is used to power CPUCLK clocks to the processor
module. 2.5V signalling is compliant to JEDEC standard 8-X. The
rest of the circuitry is powered by a 3.3V supply.
Key features, such as power-management and spread-spectrum
functions, are fully supported. PWRDWN# signal will turn off all
internal circuits and keep all outputs to a low state, making the
power consumption less than 100碌A(chǔ). For less stringent power
requirements, CPUSTOP# will turn off CPUCLK and 3V66 outputs
instantaneously. Spread spectrum function can be optionally disabled
by pulling SPREAD# pin to a HIGH state.
Pin Configuration
VSS
REF0
REF1
VDD3V
XTAL_IN
XTAL_OUT
VSS
PCICLK_F
PCICLK1
VDD3V
PCICLK2
PCICLK3
VSS
PCICLK4
PCICLK5
VDD3V
PCICLK6
PCICLK7
VSS
VSS
3V66_0
3V66_1
VDD3V
VSS
NC
NC
VDD3V
SEL133/100#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
VDD2V
APIC2
APIC1
APIC0
VSS
VDD2V
NC
NC
VSS
2.5V
Supply
VDD2V
CPUCLK3
CPUCLK2
VSS
VDD2V
CPUCLK1
CPUCLK0
VSS
VDD3V
VSS
PCISTOP#
CPUSTOP#
PWRDWN#
SPREAD#
SEL1
SEL0
VDD3V
48MHz
VSS
Block Diagram
XTAL_IN
XTAL_OUT
REF
OSC
2
REF[0:1]
3
APIC[0:2]
56-Pin
V
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
47
SEL0,1
SPREAD#
SEL100/33#
PLL1
CPUSTOP#
Div
PCISTOP#
4
CPUCLK[0:3]
7
PCICLK[1:7]
PWRDWN#
Div
PLL2
PCICLK_F
2
3V66MHz
48MHz
350
PS8415
07/23/99

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