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PI6C110EV Datasheet

  • PI6C110EV

  • CPU System Clock Generator

  • 15頁

  • ETC

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PI6C110E
Clock Solution for 133 MHz
Celeron/Pentium II/III Processors
Features
聲 3 of 2.5V 66/100/133 MHz CPU (CPU[0-2])
聲 2 of 2.5V 33 MHz APIC (APIC[0-1])
聲 9 of 3.3V 100/133 MHz SDRAM (SDRAM[0-7], DCLK)
聲 8 of 3.3V 33 MHz PCI (PCI[0-7])
聲 2 of 3.3V 66 MHz (3V66 [0-1])
聲 2 of 3.3V 48 MHz (48MHz [0-1])
聲 1 of 3.3V 14.3 MHz (REF)
聲 Selectable CPU and SDRAM clocks (on power up only)
聲 Power down function using PWR_DWN#
聲 Spread Spectrum Enable/Disable by I
2
C
聲 I
2
C interface to turn off unused clocks
聲 56 pin SSOP package (V)
Description
Pericom PI6C110E integrates a dual PLL clock generator, SDRAM
buffer and I
2
C interface. The clock generator section comprised
of an oscillator, 2 low jitter phased locked loop, skew control, and
power down logic. The SDRAM buffers are high speed and low
skew to handle data transfers in excess of 133 MHz.
When Spread Spectrum mode is enabled, all clock outputs are
modulated except for REF and 48 MHz[0-1] outputs. These clocks
are down spread linearly (triangular modulation) by +0%, 聳0.6%.
To minimize power consumption and EMI radiation some unused
outputs can be turned off. Two wire I
2
C interface is used to enable/
disable Spread Spectrum mode, and to turned off PCI clocks, CPU
clocks, and 48 MHz clocks.
For low power sleep mode, the entire device can be placed to power
down mode. Driving the PWR_DWN# to low state disables the
entire chip. In this state the crystal oscillator, and both PLLs are
turned off. Furthermore, all outputs are deactivated to low state, all
inputs are inactive except for PWR_DWN#.
Block Diagram
XIN
REF
XOUT
OSC
REF
Pin Configuration
REF/SEL2
V
DD3.3
XTAL_IN
XTAL_OUT
V
SS3.3
V
SS3.3
3V66 0
3V66 1
V
DD3.3
V
DD3.3
PCI 0
PCI 1
PCI 2
V
SS3.3
PCI 3
PCI 4
V
SS3.3
PCI 5
PCI 6
PCI 7
V
DD3.3
V
DDA
V
SSA
V
SS3.3
48MHz0
48MHz1
V
DD3.3
SEL0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
2.5V
54
53
52
51
2.5V
50
49
48
47
46
45
44
43
42
41
40
39
3.3V
38
37
36
35
34
33
32
31
30
29
V
SS2.5
APIC0
APIC1
V
DD2.5
CPU 0
V
DD2.5
CPU 1
CPU 2
V
SS2.5
V
SS3.3
SDRAM0
SDRAM1
V
DD3.3
SDRAM2
SDRAM3
V
SS3.3
SDRAM4
SDRAM5
V
DD3.3
SDRAM6
SDRAM7
V
SS3.3
DCLK
V
DD3.3
PWR_DWN#
SCLK
SDATA
SEL1
3.3V
3
8
CPU 0-2
SDRAM 0-7
DCLK
3.3V
PLL1
8
PCI 0-7
2
APIC 0-1
2
3V66 0-1
2
56-Pin
V
(V56)
3.3V
PLL2
48 MHz 0-1
3.3V
All trademarks are of their respective companies.
1
PS8410
08/11/99

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