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PI6C105H Datasheet

  • PI6C105H

  • CPU System Clock Generator

  • 15頁

  • ETC

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PI6C105
Precision Clock Synthesizer
for Mobile PCs
Features
鈥?/div>
Two copies of CPU clock with V
DD
of 2.5V 鹵5%
鈥?/div>
100 MHz or 66 MHz operation
鈥?/div>
Six copies PCI clock (synchronous with CPU clock) 3.3V
鈥?/div>
One copy of Ref. clock @ 14.31818 MHz (3.3V
TTL
)
鈥?/div>
48 MHz USB Clock, 24 MHz Super I/O clock
鈥?/div>
I
2
C Serial Configuration Interface
鈥?/div>
Spread Spectrum Modulation for CPUCLK, and PCICLK
鈥?/div>
Low-cost 14.31818 MHz crystal oscillator input
鈥?/div>
Power management control
鈥?/div>
Isolated core V
DD
, V
SS
pins for noise reduction
鈥?/div>
28-pin SSOP and SOIC package (H)
Description
The PI6C105 is a high-speed, low-noise clock generator designed
to work with the PI6C18x family of clock buffers to meet all clock
needs for Mobile Intel Architecture platforms. CPU and chipset
clock frequencies of 66.6 MHz and 100 MHz are supported.
Split supplies of 3.3V and 2.5V are used. The 3.3V power supply
powers a portion of the I/O and the core. The 2.5V is used to power
the remaining outputs. 2.5V signaling follows JEDEC standard
8-X. Power sequencing of the 3.3V and 2.5V supplies is not
required.
An asynchronous PWR_DWN# signal may be used to power down
(or up) the system in an orderly manner.
Block Diagram
Pin Configuration
XTAL_IN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
V
SSREF
V
DDREF
REF
V
DDCPU
CPUCLK0
CPUCLK1
V
SSCPU
V
DDCORE
V
SSCORE
PCI_STOP#
CPU_STOP#
PWR_DWN#
S
DATA
SCLK
XTAL_IN
XTAL_OUT
Spread#
SEL100/66#
REF
OSC
2
PLL1
CPU_STOP#
DIV
I
2
C
5
REF
CPUCLK
[0:1]
XTAL_OUT
V
SSPCI
PCICLK_F
PCICLK1
PCICLK2
S
DATA
SCLK
PCICLK
[1:5]
PCICLK_F
PCICLK3
PCICLK4
V
DDPCI
PCICLK5
V
DDP
2
48M/SPREAD#
V
SSP
2
24M/SEL100/66#
28-Pin
H
23
22
21
20
19
18
17
16
15
PCI_STOP#
PLL2
梅
2
48 MHz
24 MHz
248
PS8316
03/15/99

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