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PI6C100V Datasheet

  • PI6C100V

  • CPU System Clock Generator

  • 13頁(yè)

  • ETC

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PI6C100
Precision Clock Synthesizer
for Desktop PC聮s
Features
聲
Four copies of CPU clock with V
DD
of 2.5V + 5%
聲
100 MHz or 66 MHz operation
聲
Eight copies of PCI clock, (synchronous with CPU clock) 3.3V
聲
Two copies of IO APIC clock @14.31818 MHz
聲
Two copies of 48 MHz clock
聲
Three copies of Ref. clock @14.31818 MHz (3.3V TTL)
聲
Low cost 14.31818 MHz crystal oscillator input
聲
Spread spectrum modulation of CPU and PCI clocks for
reduced EMI
聲
Power management control
聲
Isolated core V
DD
, V
SS
pins for noise reduction
聲
48-pin SSOP package (V48)
Description
The PI6C100 is a high-speed low-noise clock generator designed to
work with the PI6C180 clock buffer to meet all clock needs for Intel
Architecture platforms. CPU and chipset clock frequencies of 66.6
MHz and 100 MHz are supported.
Split supplies of 3.3V and 2.5V are used. The 3.3V power supply
powers a portion of the I/O and the core. The 2.5V is used to power
the remaining outputs. 2.5V signaling follows JEDEC standard
8-X. Power sequencing of the 3.3V and 2.5V supplies is not required.
An asynchronous PWRDWN# signal may be used to orderly power
down (or up) the system.
Block Diagram
Pin Configuration
*KBBAHI
V
DDREF
XTAL_IN
XTAL_OUT
REF
OSC
3 REF[0:2]
V
DDAPIC
V
DDCPU 0,1
4 CPUCLK[0:3]
PLL1
梅2
CPUSTOP#
V
DDPCI 0,1
7 PCICLK[1:7]
PCISTOP#
PCICLK_F
V
DD
48MHz
PLL2
2
48MHz
2 APIC0,1
SEL0,1
SPREAD#
SEL100/66#
V
SSREF
XTAL_IN
XTAL_OUT
V
SSPCI0
PCICLK_F
PCICLK1
V
DDPCI0
PCICLK2
PCICLK3
V
SSPCI1
PCICLK4
PCICLK5
V
DDPCI1
PCICLK6
PCICLK7
V
SSPCI
2
V
DDCORE0
V
SSCORE0
V
DD
48MHz
48MHz
48MHz
V
SS
48MHz
REF0
REF1
48
1
47
2
46
3
45
4
44
5
43
6
42
7
41
8
9
48-Pin
40
10
V48
39
38
11
37
12
36
13
35
14
34
15
33
16
17
32
18
31
19
30
20
29
21
28
22
27
23
26
25
24
V
DDREF
REF2
V
DDAPIC
APIC0
APIC1
V
SSAPIC
NC
V
DDCPU0
CPUCLK0
CPUCLK1
V
SSCPU0
V
DDCPU1
CPUCLK2
CPUCLK3
V
SSCPU1
V
DDCORE1
V
SSCORE1
PCISTOP#
CPUSTOP#
PWRDWN#
SPREAD#
SEL0
SEL1
SEL100/66#
198
PS8142A 10/13/98

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