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PHW7N60 Datasheet

  • PHW7N60

  • PowerMOS transistor

  • 7頁

  • PHILIPS

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Philips Semiconductors
Product specification
PowerMOS transistor
PHW7N60
GENERAL DESCRIPTION
N-channel enhancement mode
field-effect power transistor in a
plastic envelope featuring high
avalanche energy capability, stable
off-state
characteristics,
fast
switching and high thermal cycling
performance with low thermal
resistance. Intended for use in
Switched Mode Power Supplies
(SMPS), motor control circuits and
general
purpose
switching
applications.
QUICK REFERENCE DATA
SYMBOL
V
DS
I
D
P
tot
R
DS(ON)
PARAMETER
Drain-source voltage
Drain current (DC)
Total power dissipation
Drain-source on-state resistance
MAX.
600
7
147
1.2
UNIT
V
A
W
鈩?/div>
PINNING - SOT429 (TO247)
PIN
1
2
3
tab
gate
drain
source
drain
DESCRIPTION
PIN CONFIGURATION
SYMBOL
d
g
1
2
3
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
I
D
I
DM
P
D
鈭哖
D
/鈭員
mb
V
GS
E
AS
I
AS
T
j
, T
stg
Continuous drain current
Pulsed drain current
Total dissipation
Linear derating factor
Gate-source voltage
Single pulse avalanche
energy
Peak avalanche current
Operating junction and
storage temperature range
CONDITIONS
T
mb
= 25 藲C; V
GS
= 10 V
T
mb
= 100 藲C; V
GS
= 10 V
T
mb
= 25 藲C
T
mb
= 25 藲C
T
mb
> 25 藲C
V
DD
鈮?/div>
50 V; starting T
j
= 25藲C; R
GS
= 50
鈩?
V
GS
= 10 V
V
DD
鈮?/div>
50 V; starting T
j
= 25藲C; R
GS
= 50
鈩?
V
GS
= 10 V
MIN.
-
-
-
-
-
-
-
-
- 55
MAX.
7
4.5
28
147
1.176
鹵
30
570
7
150
UNIT
A
A
A
W
W/K
V
mJ
A
藲C
THERMAL RESISTANCES
SYMBOL
R
th j-mb
R
th j-a
PARAMETER
Thermal resistance junction to
mounting base
Thermal resistance junction to
ambient
CONDITIONS
MIN.
-
-
TYP.
-
45
MAX.
0.85
-
UNIT
K/W
K/W
June 1997
1
Rev 1.000

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