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PHW35NQ20T Datasheet

  • PHW35NQ20T

  • N-channel TrenchMOS transistor

  • 7頁

  • PHILIPS

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Philips Semiconductors
Product specification
N-channel TrenchMOS鈩?transistor
PHW35NQ20T
FEATURES
鈥?/div>
鈥橳rench鈥?/div>
technology
鈥?Very low on-state resistance
鈥?Fast switching
鈥?Low thermal resistance
SYMBOL
d
QUICK REFERENCE DATA
V
DSS
= 200 V
I
D
= 35 A
g
R
DS(ON)
鈮?/div>
70 m鈩?/div>
s
GENERAL DESCRIPTION
N-channel enhancement mode
field-effect power transistor in a
plastic envelope using 鈥檛rench鈥?/div>
technology. The device has very
low on-state resistance. It is
intended for use in dc to dc
converters and general purpose
switching applications.
The PHW35NQ20T is supplied in
the SOT429 (TO247) conventional
leaded package.
PINNING
PIN
1
2
3
tab
gate
drain
source
drain
DESCRIPTION
SOT429 (TO247)
1
2
3
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
V
DSS
V
DGR
V
GS
I
D
I
DM
P
D
T
j
, T
stg
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Continuous drain current
Pulsed drain current
Total power dissipation
Operating junction and
storage temperature
CONDITIONS
T
j
= 25 藲C to 175藲C
T
j
= 25 藲C to 175藲C; R
GS
= 20 k鈩?/div>
T
mb
= 25 藲C
T
mb
= 100 藲C
T
mb
= 25 藲C
T
mb
= 25 藲C
MIN.
-
-
-
-
-
-
-
- 55
MAX.
200
200
鹵
20
35
25
140
250
175
UNIT
V
V
V
A
A
A
W
藲C
AVALANCHE ENERGY LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
E
AS
Non-repetitive avalanche
energy
Non-repetitive avalanche
current
CONDITIONS
Unclamped inductive load, I
AS
= 35 A;
t
p
= 100
碌s;
T
j
prior to avalanche = 25藲C;
V
DD
鈮?/div>
50 V; R
GS
= 50
鈩?
V
GS
= 10 V; refer
to fig:15
MIN.
-
MAX.
462
UNIT
mJ
I
AS
-
35
A
August 1999
1
Rev 1.000

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