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PHT6N03LT Datasheet

  • PHT6N03LT

  • TrenchMOS transistor Logic level FET

  • 56.85KB

  • 6頁

  • PHILIPS

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Philips Semiconductors
Product specification
TrenchMOS鈩?transistor
Logic level FET
FEATURES
鈥?/div>
鈥橳rench鈥?/div>
technology
鈥?Very low on-state resistance
鈥?Fast switching
鈥?Stable off-state characteristics
鈥?High thermal cycling performance
鈥?Surface mounting package
PHT6N03LT
SYMBOL
d
QUICK REFERENCE DATA
V
DSS
= 30 V
I
D
= 5.9 A
g
s
R
DS(ON)
鈮?/div>
30 m鈩?(V
GS
= 5 V)
R
DS(ON)
鈮?/div>
28 m鈩?(V
GS
= 10 V)
SOT223
DESCRIPTION
GENERAL DESCRIPTION
N-channel enhancement mode
logic level field-effect power
transistor
using
鈥檛rench鈥?/div>
technology. The device has very
low on-state resistance. It is
intended for use in dc to dc
converters and general purpose
switching applications.
The PHT6N03LT is supplied in the
SOT223
surface
mounting
package.
PINNING
PIN
1
2
3
tab
gate
drain
source
drain
4
1
2
3
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
V
DSS
V
DGR
V
GS
I
D
I
DM
P
D
T
j
, T
stg
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Continuous drain current
Pulsed drain current
Total power dissipation
Operating junction and
storage temperature
CONDITIONS
T
j
= 25 藲C to 150藲C
T
j
= 25 藲C to 150藲C; R
GS
= 20 k鈩?/div>
T
amb
= 25 藲C; V
GS
= 10 V
T
amb
= 100 藲C; V
GS
= 10 V
T
amb
= 25 藲C
MIN.
-
-
-
-
-
-
-
- 55
MAX.
30
30
鹵
13
5.9
4.1
23.6
1.8
150
UNIT
V
V
V
A
A
A
W
藲C
ESD LIMITING VALUE
SYMBOL PARAMETER
V
C
Electrostatic discharge
capacitor voltage, all pins
CONDITIONS
Human body model (100 pF, 1.5 k鈩?
MIN.
-
MAX.
2
UNIT
kV
THERMAL RESISTANCES
SYMBOL PARAMETER
R
th j-sp
R
th j-a
Thermal resistance junction
to solder point
Thermal resistance junction
to ambient
CONDITIONS
mounted on any pcb
mounted on test pcb of fig:17
MIN.
-
-
TYP. MAX. UNIT
-
70
15
-
K/W
K/W
January 1998
1
Rev 1.300

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