Philips Semiconductors
Objective specification
PowerMOS transistor
PHT1N52S
GENERAL DESCRIPTION
N-channel enhancement mode
field-effect power transistor in a
plastic envelope suitable for surface
mounting featuring high avalanche
energy capability, stable blocking
voltage, fast switching and high
thermal
cycling
performance.
Intended for use in Compact Fluor-
escent Lights (CFL) and general
purpose switching applications.
QUICK REFERENCE DATA
SYMBOL
V
DS
I
D
P
tot
R
DS(ON)
PARAMETER
Drain-source voltage
Drain current (DC)
Total power dissipation
Drain-source on-state resistance
MAX.
520
0.6
1.8
10
UNIT
V
A
W
鈩?/div>
PINNING - SOT223
PIN
1
2
3
4
gate
drain
source
drain (tab)
DESCRIPTION
PIN CONFIGURATION
4
SYMBOL
d
g
1
2
3
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
V
DS
V
DGR
鹵V
GS
I
D
I
DM
I
DR
I
DRM
P
tot
T
stg
T
j
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Drain current (DC)
Drain current (pulse peak
value)
Source-drain diode current
(DC)
Source-drain diode current
(pulse peak value)
Total power dissipation
Storage temperature
Junction temperature
CONDITIONS
R
GS
= 20 k鈩?/div>
T
sp
= 25 藲C
T
sp
= 100 藲C
T
sp
= 25 藲C
T
sp
= 25 藲C
T
sp
= 25 藲C
T
sp
= 25 藲C
MIN.
-
-
-
-
-
-
-
-
-
-55
-
MAX.
520
520
30
0.6
0.5
2.4
0.6
2.4
1.8
150
150
UNIT
V
V
V
A
A
A
A
A
W
藲C
藲C
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER
W
DSS
CONDITIONS
MIN.
MAX.
UNIT
Drain-source non-repetitive I
D
= 1 A ; V
DD
鈮?/div>
50 V ; V
GS
= 10 V ;
unclamped inductive turn-off R
GS
= 50
鈩?/div>
energy
T
j
= 25藲C prior to surge
T
j
= 100藲C prior to surge
Drain-source repetitive
I
D
= 1 A ; V
DD
鈮?/div>
50 V ; V
GS
= 10 V ;
unclamped inductive turn-off R
GS
= 50
鈩?/div>
; T
j
鈮?/div>
150 藲C
energy
W
DSR1
-
-
-
25
10
3.6
mJ
mJ
mJ
1. Pulse width and frequency limited by T
j(max)
February 1998
1
Rev 1.000
PHT1N52S相關(guān)型號PDF文件下載
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